12-Bit, 125 MSPS a TxDAC D/A Converter AD9762 FUNCTIONAL BLOCK DIAGRAM FEATURES Member of Pin-Compatible TxDAC Product Family +5V 125 MSPS Update Rate 0.1 F 12-Bit Resolution Excellent Spurious Free Dynamic Range Performance REFLO COMP1 AVDD ACOM SFDR to Nyquist 5 MHz Output: 70 dBc +1.20V REF AD9762 50pF Differential Current Outputs: 2 mA to 20 mA 0.1 F REFIO 0.1 F CURRENT COMP2 Power Dissipation: 175 mW 5 V to 45 mW 3 V SOURCE FS ADJ Power-Down Mode: 25 mW 5 V ARRAY R SET On-Chip 1.20 V Reference +5V DVDD IOUTA Single +5 V or +3 V Supply Operation SEGMENTED LSB DCOM IOUTB SWITCHES SWITCHES Package: 28-Lead SOIC and TSSOP CLOCK Edge-Triggered Latches CLOCK LATCHES SLEEP APPLICATIONS DIGITAL DATA INPUTS (DB11DB0) Communication Transmit Channel: Basestations (Single/Multichannel Applications) ADSL/HFC Modems Differential current outputs are provided to support single- Direct Digital Synthesis (DDS) ended or differential applications. Matching between the two Instrumentation current outputs ensures enhanced dynamic performance in a differential output configuration. The current outputs may be PRODUCT DESCRIPTION tied directly to an output resistor to provide two complemen- The AD9762 is the 12-bit resolution member of the TxDAC tary, single-ended voltage outputs or fed directly into a trans- series of high performance, low power CMOS digital-to-analog former. The output voltage compliance range is 1.25 V. converters (DACs). The TxDAC family which consists of pin The on-chip reference and control amplifier are configured for compatible 8-, 10-, 12-, and 14-bit DACs is specifically opti- maximum accuracy and flexibility. The AD9762 can be driven mized for the transmit signal path of communication systems. by the on-chip reference or by a variety of external reference All of the devices share the same interface options, small outline voltages. The internal control amplifier which provides a wide package and pinout, thus providing an upward or downward (>10:1) adjustment span allows the AD9762 full-scale current component selection path based on performance, resolution and to be adjusted over a 2 mA to 20 mA range while maintaining cost. The AD9762 offers exceptional ac and dc performance excellent dynamic performance. Thus, the AD9762 may oper- while supporting update rates up to 125 MSPS. ate at reduced power levels or be adjusted over a 20 dB range to The AD9762s flexible single-supply operating range of 2.7 V to provide additional gain ranging capabilities. 5.5 V and low power dissipation are well suited for portable and The AD9762 is available in 28-lead SOIC and TSSOP pack- low power applications. Its power dissipation can be further ages. It is specified for operation over the industrial tempera- reduced to a mere 45 mW without a significant degradation in ture range. performance by lowering the full-scale current output. Also, a power-down mode reduces the standby power dissipation to PRODUCT HIGHLIGHTS approximately 25 mW. 1. The AD9762 is a member of the TxDAC product family which The AD9762 is manufactured on an advanced CMOS process. provides an upward or downward component selection path A segmented current source architecture is combined with a based on resolution (8 to 14 bits), performance and cost. proprietary switching technique to reduce spurious components 2. Manufactured on a CMOS process, the AD9762 uses a pro- and enhance dynamic performance. Edge-triggered input prietary switching technique that enhances dynamic perfor- latches and a 1.2 V temperature compensated bandgap refer- mance beyond what was previously attainable by higher ence have been integrated to provide a complete monolithic power/cost bipolar or BiCMOS devices. DAC solution. Flexible supply options support +3 V and +5 V 3. On-chip, edge-triggered input CMOS latches interface readily CMOS logic families. to +3 V and +5 V CMOS logic families. The AD9762 can The AD9762 is a current-output DAC with a nominal full-scale support update rates up to 125 MSPS. output current of 20 mA and > 100 k output impedance. 4. A flexible single-supply operating range of 2.7 V to 5.5 V and TxDAC is a registered trademark of Analog Devices, Inc. a wide full-scale current adjustment span of 2 mA to 20 mA allow the AD9762 to operate at reduced power levels. REV. B 5. The current output(s) of the AD9762 can be easily config- ured for various single-ended or differential circuit topologies. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties Tel: 781/329-4700 World Wide Web Site: AD9762SPECIFICATIONS (T to T , AVDD = +5 V, DVDD = +5 V, I = 20 mA, unless otherwise noted) DC SPECIFICATIONS MIN MAX OUTFS Parameter Min Typ Max Units RESOLUTION 12 Bits 1 DC ACCURACY Integral Linearity Error (INL) T = +25C 2.5 0.75 +2.5 LSB A T to T 4.0 1.0 +4.0 LSB MIN MAX Differential Nonlinearity (DNL) T = +25C 1.5 0.5 +1.5 LSB A T to T 2.0 0.75 +2.0 LSB MIN MAX ANALOG OUTPUT Offset Error 0.025 +0.025 % of FSR Gain Error (Without Internal Reference) 10 2 +10 % of FSR Gain Error (With Internal Reference) 10 1 +10 % of FSR 2 Full-Scale Output Current 2.0 20.0 mA Output Compliance Range 1.0 +1.25 V Output Resistance 100 k Output Capacitance 5 pF REFERENCE OUTPUT Reference Voltage 1.08 1.20 1.32 V 3 Reference Output Current 100 nA REFERENCE INPUT Input Compliance Range 0.1 1.25 V Reference Input Resistance 1 M 4 Small Signal Bandwidth (w/o C ) 1.4 MHz COMP1 TEMPERATURE COEFFICIENTS Offset Drift 0 ppm of FSR/C Gain Drift (Without Internal Reference) 50 ppm of FSR/C Gain Drift (With Internal Reference) 100 ppm of FSR/C Reference Voltage Drift 50 ppm/C POWER SUPPLY Supply Voltages 5 AVDD 2.7 5.0 5.5 V DVDD 2.7 5.0 5.5 V Analog Supply Current (I)2530mA AVDD 6 Digital Supply Current (I ) 1.5 2 mA DVDD ) 8.5 mA Supply Current Sleep Mode (I AVDD 6 Power Dissipation (5 V, I = 20 mA) 133 160 mW OUTFS 7 Power Dissipation (5 V, I = 20 mA) 190 mW OUTFS 7 (3 V, I = 2 mA) 45 mW Power Dissipation OUTFS Power Supply Rejection RatioAVDD 0.4 +0.4 % of FSR/V Power Supply Rejection RatioDVDD 0.025 +0.025 % of FSR/V OPERATING RANGE 40 +85 C NOTES 1 Measured at IOUTA, driving a virtual ground. 2 Nominal full-scale current, I , is 32 the I current. OUTFS REF 3 Use an external buffer amplifier to drive any external load. 4 Reference bandwidth is a function of external cap at COMP1 pin and signal level. Refer to Figure 41. 5 For operation below 3 V, it is recommended that the output current be reduced to 12 mA or less to maintain optimum performance. 6 Measured at f = 25 MSPS and f = 1.0 MHz. CLOCK OUT 7 Measured as unbuffered voltage output into 50 R at IOUTA and IOUTB, f = 100 MSPS and f = 40 MHz. LOAD CLOCK OUT Specifications subject to change without notice. 2 REV. B