10-/12-/14-Bit, 125 MSPS Dual TxDAC+ Digital-to-Analog Converters Data Sheet AD9763/AD9765/AD9767 FEATURES FUNCTIONAL BLOCK DIAGRAM DVDD1/ DCOM1/ 10-/12-/14-bit dual transmit digital-to-analog converters (DACs) DVDD2 DCOM2 AVDD ACOM CLK1 125 MSPS update rate I OUTA1 1 1 Excellent SFDR to Nyquist 5 MHz output: 75 dBc PORT1 LATCH DAC I OUTB1 Excellent gain and offset matching: 0.1% REFIO Fully independent or single-resistor gain control FSADJ1 REFERENCE WRT1/IQWRT FSADJ2 AD9763/ Dual-port or interleaved data DIGITAL GAINCTRL INTERFACE AD9765/ WRT2/IQSEL On-chip 1.2 V reference AD9767 BIAS SLEEP GENERATOR 5 V or 3.3 V operation Power dissipation: 380 mW 5 V I 2 2 OUTA2 PORT2 LATCH DAC Power-down mode: 50 mW 5 V I OUTB2 48-lead LQFP MODE CLK2/IQ RESET Figure 1. APPLICATIONS Communications The DACs utilize a segmented current source architecture Base stations combined with a proprietary switching technique to reduce Digital synthesis glitch energy and maximize dynamic accuracy. Each DAC provides Quadrature modulation differential current output, thus supporting single-ended or dif- 3D ultrasound ferential applications. Both DACs of the AD9763, AD9765, or AD9767 can be simultaneously updated and can provide a GENERAL DESCRIPTION nominal full-scale current of 20 mA. The full-scale currents The AD9763/AD9765/AD9767 are dual-port, high speed, between each DAC are matched to within 0.1%. 2-channel, 10-/12-/14-bit CMOS DACs. Each part integrates The AD9763/AD9765/AD9767 are manufactured on an two high quality TxDAC+ cores, a voltage reference, and digital advanced, low cost CMOS process. They operate from a single interface circuitry into a small 48-lead LQFP. The AD9763/ supply of 3.3 V to 5 V and consume 380 mW of power. AD9765/AD9767 offer exceptional ac and dc performance while supporting update rates of up to 125 MSPS. PRODUCT HIGHLIGHTS The AD9763/AD9765/AD9767 have been optimized for 1. The AD9763/AD9765/AD9767 are members of a pin- processing I and Q data in communications applications. The compatible family of dual TxDACs providing 8-, 10-, 12-, digital interface consists of two double-buffered latches as well and 14-bit resolution. as control logic. Separate write inputs allow data to be written to 2. Dual 10-/12-/14-Bit, 125 MSPS DACs. A pair of high the two DAC ports independent of one another. Separate clocks performance DACs for each part is optimized for low control the update rate of the DACs. distortion performance and provides flexible transmission of I and Q information. A mode control pin allows the AD9763/AD9765/AD9767 to 3. Matching. Gain matching is typically 0.1% of full scale, and interface to two separate data ports, or to a single interleaved offset error is better than 0.02%. high speed data port. In interleaving mode, the input data 4. Low Power. Complete CMOS dual DAC function operates on stream is demuxed into its original I and Q data and then 380 mW from a 3.3 V to 5 V single supply. The DAC full-scale latched. The I and Q data is then converted by the two DACs current can be reduced for lower power operation, and a sleep and updated at half the input data rate. mode is provided for low power idle periods. The GAINCTRL pin allows two modes for setting the full-scale 5. On-Chip Voltage Reference. The AD9763/AD9765/AD9767 current (I ) of the two DACs. I for each DAC can be set OUTFS OUTFS each include a 1.20 V temperature-compensated band gap independently using two external resistors, or I for both OUTFS voltage reference. DACs can be set by using a single external resistor. See the 6. Dual 10-/12-/14-Bit Inputs. The AD9763/AD9765/AD9767 Gain Control Mode section for important date code each feature a flexible dual-port interface, allowing dual or information on this feature. interleaved input data. Rev. G Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 1999-2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 00617-001AD9763/AD9765/AD9767 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Digital Inputs .............................................................................. 24 Applications....................................................................................... 1 DAC Timing................................................................................ 24 General Description ......................................................................... 1 Sleep Mode Operation............................................................... 26 Functional Block Diagram .............................................................. 1 Power Dissipation....................................................................... 26 Product Highlights ........................................................................... 1 Applying the AD9763/AD9765/AD9767.................................... 28 Revision History ............................................................................... 2 Output Configurations .............................................................. 28 Specifications..................................................................................... 5 Differential Coupling Using a Transformer............................ 28 DC Specifications ......................................................................... 5 Differential Coupling Using an Op Amp................................ 28 Dynamic Specifications ............................................................... 6 Single-Ended, Unbuffered Voltage Output............................. 29 Digital Specifications ................................................................... 7 Single-Ended, Buffered Voltage Output Configuration........ 29 Absolute Maximum Ratings............................................................ 8 Power and Grounding Considerations.................................... 29 Thermal Resistance ...................................................................... 8 Applications Information .............................................................. 31 ESD Caution.................................................................................. 8 VDSL Example Applications Using the AD9765 and AD9767 ................................................................ 31 Pin Configuration and Function Descriptions............................. 9 Quadrature Amplitude Modulation (QAM) Example Using Typical Performance Characteristics ........................................... 11 the AD9763 ................................................................................. 32 AD9763........................................................................................ 11 CDMA ......................................................................................... 33 AD9765........................................................................................ 14 Evaluation Board ............................................................................ 34 AD9767........................................................................................ 17 General Description................................................................... 34 Terminology .................................................................................... 20 Schematics................................................................................... 34 Theory of Operation ...................................................................... 21 Evaluation Board Layout........................................................... 40 Functional Description.............................................................. 21 Outline Dimensions....................................................................... 42 Reference Operation .................................................................. 22 Ordering Guide .......................................................................... 42 Gain Control Mode .................................................................... 22 Setting the Full-Scale Current................................................... 22 DAC Transfer Function ............................................................. 23 Analog Outputs........................................................................... 23 REVISION HISTORY Revision History: AD9763/AD9765/AD9767 Revision History: AD9763 8/11Rev. F to Rev. G 1/08Rev. D to Rev. E Changes to Gain Control Mode Section and Setting the Full- Combined with AD9765 and AD9767 Data Sheets.......Universal Scale Current Section..................................................................... 22 Changes to Figure 1...........................................................................1 Changes to DAC Transfer Function Section............................... 23 Changes to Applications Section.....................................................1 Changes to Power Supply Rejection Section............................... 29 Changes to Timing Diagram Section .............................................7 Added Figure 4 and Figure 5............................................................9 6/09Rev. E to Rev. F Changes to Table 6.......................................................................... 10 Replaced Figure 86 to Figure 90 with Figure 86 to Figure 91, Change to Typical Performance Characteristics Section Deleted Original Figure 91 to Figure 94...................................... 34 Conditions Statement .................................................................... 11 Added Figure 23 to Figure 56 ....................................................... 14 1/08Revision E: Initial Combined Version Added Note to Figure 58 ............................................................... 20 Changes to Functional Description Section ............................... 22 Changes to Figure 59 and Figure 60............................................. 22 Changes to Gain Control Mode Section ..................................... 22 Rev. G Page 2 of 44