14-Bit, 160 MSPS TxDAC+ with 2 Interpolation Filter AD9772A FEATURES FUNCTIONAL BLOCK DIAGRAM CLKCOM CLKVDD MOD0 MOD1 RESET PLLLOCK DIV0 DIV1 Single 3.1 V to 3.5 V supply AD9772A 14-bit DAC resolution and input data width CLK+ PLLCOM CLOCK DISTRIBUTION PLL CLOCK 160 MSPS input data rate CLK AND MODE SELECT MULTIPLIER LPF 67.5 MHz reconstruction pass band 160 MSPS FILTER MUX PLLVDD 1 1/2 2/4 CONTROL CONTROL 74 dBc SFDR 25 MHz 2 interpolation filter with high- or low-pass response I DATA ZERO- OUTA 2 FIR EDGE- STUFF 14-BIT DAC INPUTS INTER- 73 dB image rejection with 0.005 dB pass-band ripple TRIGGERED I (DB13 TO MUX OUTB POLATION LATCHES DB0) FILTER Zero-stuffing option for enhanced direct IF performance REFIO 1.2V REFERENCE Internal 2/4 clock multiplier SLEEP FSADJ AND CONTROL AMP 250 mW power dissipation 13 mW with power-down mode 48-lead LQFP package DCOM DVDD ACOM AVDD REFLO Figure 1. APPLICATIONS Communication transmit channel W-CDMA base stations, multicarrier base stations, direct IF synthesis, wideband cable systems Instrumentation GENERAL DESCRIPTION The AD9772A is a single-supply, oversampling, 14-bit digital- The AD9772A can reconstruct full-scale waveforms with band- to-analog converter (DAC) optimized for baseband or IF widths of up to 67.5 MHz while operating at an input data rate of 160 MSPS. The 14-bit DAC provides differential current waveform reconstruction applications requiring exceptional outputs to support differential or single-ended applications. dynamic range. Manufactured on an advanced CMOS process, it integrates a complete, low distortion 14-bit DAC with a 2 A segmented current source architecture is combined with a digital interpolation filter and clock multiplier. The on-chip PLL proprietary switching technique to reduce spurious components clock multiplier provides all the necessary clocks for the digital and enhance dynamic performance. Matching between the two filter and the 14-bit DAC. A flexible differential clock input current outputs ensures enhanced dynamic performance in a allows for a single-ended or differential clock driver for differential output configuration. The differential current optimum jitter performance. outputs can be fed into a transformer or a differential op amp topology to obtain a single-ended output voltage using an For baseband applications, the 2 digital interpolation filter appropriate resistive load. provides a low-pass response, thus providing as much as a threefold reduction in the complexity of the analog reconstruc- The on-chip band gap reference and control amplifier are con- tion filter. It does so by multiplying the input data rate by a figured for maximum accuracy and flexibility. The AD9772A factor of 2 while suppressing the original upper in-band image can be driven by the on-chip reference or by a variety of by more than 73 dB. For direct IF applications, the 2 digital external reference voltages. The full-scale current of the interpolation filter response can be reconfigured to select the AD9772A can be adjusted over a 2 mA to 20 mA range, thus upper in-band image (that is, the high-pass response) while providing additional gain-ranging capabilities. suppressing the original baseband image. To increase the signal The AD9772A is available in a 48-lead LQFP package and is level of the higher IF images and their pass-band flatness in specified for operation over the industrial temperature range of direct IF applications, the AD9772A also features a zero-stuffing 40C to +85C. option in which the data following the 2 interpolation filter is upsampled by a factor of 2 by inserting midscale data samples. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 02253-001AD9772A TABLE OF CONTENTS Features .............................................................................................. 1 DAC Transfer Function ............................................................. 22 Applications....................................................................................... 1 Reference Operation .................................................................. 22 Functional Block Diagram .............................................................. 1 Reference Control Amplifier .................................................... 23 General Description ......................................................................... 1 Analog Outputs .......................................................................... 23 Revision History ............................................................................... 2 Digital Inputs/Outputs .............................................................. 24 Product Highlights ........................................................................... 3 Sleep Mode Operation............................................................... 25 Specifications..................................................................................... 4 Power Dissipation....................................................................... 25 DC Specifications ......................................................................... 4 Applying the AD9772A ................................................................. 26 Dynamic Specifications ............................................................... 6 Output Configurations .............................................................. 26 Digital Specifications ................................................................... 7 Differential Coupling Using a Transformer ............................... 26 Digital Filter Specifications ......................................................... 8 Differential Coupling Using an Op Amp................................ 26 Absolute Maximum Ratings............................................................ 9 Single-Ended, Unbuffered Voltage Output............................. 26 Thermal Characteristics .............................................................. 9 Single-Ended, Buffered Voltage Output.................................. 27 ESD Caution.................................................................................. 9 Power and Grounding Considerations.................................... 27 Pin Configuration and Function Descriptions........................... 10 Applications Information .............................................................. 29 Terminology .................................................................................... 12 Multicarrier ................................................................................. 29 Typical Performance Characteristics ........................................... 14 Baseband Single-Carrier Applications .................................... 30 Theory of Operation ...................................................................... 17 Direct IF....................................................................................... 30 Functional Description.............................................................. 17 AD9772A Evaluation Board ......................................................... 32 Digital Modes of Operation ...................................................... 17 Schematics................................................................................... 33 PLL Clock Multiplier Operation .............................................. 19 Evaluation Board Layout........................................................... 35 Synchronization of Clock/Data Outline Dimensions ....................................................................... 38 Using Reset with PLL Disabled................................................. 21 Ordering Guide .......................................................................... 38 DAC Operation........................................................................... 22 Change to Digital Filter Specifications ...........................................5 REVISION HISTORY Ordering Guide Updated .................................................................6 2/08Rev. B to Rev. C Change to Pin Function Descriptions ............................................7 Changes to DVDD Parameter......................................................... 4 Change to Figure 13a and Figure 13b.......................................... 15 Changes to PLL Clock Enabled Parameter ................................... 7 Change to Digital Inputs/Outputs................................................ 18 Changes to PLL Clock Disabled Parameter .................................. 7 Change to Sleep Mode Operation ................................................ 19 Changes to Table 8.......................................................................... 10 Change to Figure 22 ....................................................................... 19 Changes to Functional Description ............................................. 17 Change to Figure 23 ....................................................................... 19 Change to Power Dissipation Section.......................................... 25 Change to Power and Ground Considerations .......................... 21 Changes to Power and Grounding Considerations Section ..... 27 Change to Figure 29 ....................................................................... 21 Change to Figure 53 ....................................................................... 29 Update to Outline Dimensions..................................................... 30 Change to Direct IF Section.......................................................... 30 Changes to Figure 61...................................................................... 34 3/02Rev. 0 to Rev. A Updated Outline Dimensions ....................................................... 38 Edits to Digital Specifications..........................................................4 Changes to Ordering Guide .......................................................... 38 Edits to Absolute Maximum Ratings..............................................6 Change to TPC 11 .......................................................................... 10 6/03Rev. A to Rev. B Change to Figure 9 Caption .......................................................... 14 Change to Features .......................................................................... 1 Change to Figure 13a and Figure 13b.......................................... 15 Change to DC Specifications .......................................................... 2 Rev. C Page 2 of 40