12-Bit, 160 MSPS, 2/4/8 Interpolating Dual TxDAC D/A Converter AD9773 FEATURES Versatile input data interface Twos complement/straight binary data coding 12-bit resolution, 160 MSPS/400 MSPS Dual-port or single-port interleaved input data input/output data rate Single 3.3 V supply operation Selectable 2/4/8 interpolating filter Power dissipation: typical 1.2 W 3.3 V Programmable channel gain and offset adjustment On-chip 1.2 V reference f /2, f /4, f /8 digital quadrature modulation capability S S S 80-lead thin quad flat package, exposed pad (TQFP EP) Direct IF transmission mode for 70 MHz + IFs Enables image rejection architecture APPLICATIONS Fully compatible SPI port Communications Excellent ac performance Analog quadrature modulation architecture SFDR 69 dBc 2 MHz to 35 MHz 3G, multicarrier GSM, TDMA, CDMA systems WCDMA ACPR 69 dB IF = 19.2 MHz Broadband wireless, point-to-point microwave radios Internal PLL clock multiplier Instrumentation/ATE Selectable internal clock divider Versatile clock input Differential/single-ended sine wave or TTL/CMOS/LVPECL compatible FUNCTIONAL BLOCK DIAGRAM IDAC COS AD9773 HALF- HALF- HALF- GAIN OFFSET BAND BAND BAND DAC DAC FILTER1* FILTER2* FILTER3* DATA SIN ASSEMBLER IMAGE 12 16 16 16 16 REJECTION/ I I/Q DAC f /2, 4, 8 DUAL DAC LATCH GAIN/OFFSET DAC MODE REGISTERS I AND Q BYPASS NONINTERLEAVED MUX OR INTERLEAVED SIN 16 16 16 16 DATA Q LATCH 12 FILTER COS BYPASS WRITE MUX MUX CONTROL IDAC I SELECT OUT /2 (f ) DAC CLOCK OUT /2 /2 /2 SPI INTERFACE AND PRESCALER DIFFERENTIAL CONTROL REGISTERS CLK PHASE DETECTOR AND VCO * HALF-BAND FILTERS ALSO CAN BE CONFIGURED FOR ZERO STUFFING ONLY PLL CLOCK MULTIPLIER AND CLOCK DIVIDER Figure 1. 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VREF IOFFSET 02857-001AD9773 TABLE OF CONTENTS Features .............................................................................................. 1 Two-Port Data Input Mode ...................................................... 30 Applications....................................................................................... 1 One-/Two-Port Input Modes.................................................... 30 Functional Block Diagram .......................................................... 1 PLL Enabled, Two-Port Mode .................................................. 30 Table of Contents.............................................................................. 2 DATACLK Inversion.................................................................. 31 Revision History ........................................................................... 2 DATACLK Driver Strength....................................................... 31 General Description ......................................................................... 4 PLL Enabled, One-Port Mode .................................................. 31 Product Highlights ....................................................................... 4 ONEPORTCLK Inversion......................................................... 31 Specifications..................................................................................... 5 ONEPORTCLK Driver Strength.............................................. 32 DC Specifications ......................................................................... 5 IQ Pairing .................................................................................... 32 Dynamic Specifications ............................................................... 6 PLL Disabled, Two-Port Mode................................................. 32 Digital Specifications ................................................................... 7 PLL Disabled, One-Port Mode................................................. 32 Digital Filter Specifications ......................................................... 8 Digital Filter Modes ................................................................... 33 Absolute Maximum Ratings............................................................ 9 Amplitude Modulation.............................................................. 33 Thermal Characteristics .............................................................. 9 Modulation, No Interpolation .................................................. 34 ESD Caution.................................................................................. 9 Modulation, Interpolation = 2 ............................................... 35 Pin Configuration and Function Descriptions........................... 10 Modulation, Interpolation = 4 ............................................... 36 Typical Performance Characteristics ........................................... 12 Modulation, Interpolation = 8 ............................................... 37 Terminology .................................................................................... 17 Zero Stuffing ............................................................................... 38 Mode Control (Via SPI Port) .................................................... 18 Interpolating (Complex Mix Mode)........................................ 38 Register Description................................................................... 20 Operations on Complex Signals............................................... 38 Functional Description .................................................................. 22 Complex Modulation and Image Rejection of Baseband Signals .......................................................................................... 39 Serial Interface for Register Control ........................................ 22 Image Rejection and Sideband Suppression of Modulated General Operation of the Serial Interface ............................... 22 Carriers ........................................................................................ 41 Instruction Byte .......................................................................... 23 Applying the Output Configurations........................................... 46 Serial Interface Port Pin Descriptions ..................................... 23 Unbuffered Differential Output, Equivalent Circuit ............. 46 MSB/LSB Transfers..................................................................... 23 Differential Coupling Using a Transformer............................ 46 Notes on Serial Port Operation ................................................ 25 Differential Coupling Using an Op Amp................................ 47 DAC Operation........................................................................... 25 Interfacing the AD9773 with the AD8345 Quadrature 1R/2R Mode ................................................................................ 26 Modulator.................................................................................... 47 Clock Input Configurations ...................................................... 27 Evaluation Board ............................................................................ 48 Programmable PLL .................................................................... 27 Outline Dimensions....................................................................... 58 Power Dissipation....................................................................... 29 Ordering Guide .......................................................................... 58 Sleep/Power-Down Modes........................................................ 29 REVISION HISTORY Changes to Figure 108 .................................................................. 54 10/07Rev. C to Rev. D Updated Outline Dimensions ..................................................... 58 Updated Formatting ........................................................ Universal Changes to Ordering Guide......................................................... 58 Changes to Figure 32 ....................................................................22 Rev. D Page 2 of 60