Dual, 12-/14-/16-Bit,1 GSPS Digital-to-Analog Converters Data Sheet AD9776A/AD9778A/AD9779A FEATURES GENERAL DESCRIPTION Low power: 1.0 W 1 GSPS, 600 mW 500 MSPS, The AD9776A/AD9778A/AD9779A are dual, 12-/14-/16-bit, full operating conditions high dynamic range digital-to-analog converters (DACs) that Single carrier W-CDMA ACLR = 80 dBc 80 MHz IF provide a sample rate of 1 GSPS, permitting a multicarrier Analog output: adjustable 8.7 mA to 31.7 mA, generation up to the Nyquist frequency. They include features R = 25 to 50 L optimized for direct conversion transmission applications, Novel 2, 4, and 8 interpolator/coarse complex modulator including complex digital modulation and gain and offset allows carrier placement anywhere in DAC bandwidth compensation. The DAC outputs are optimized to interface Auxiliary DACs allow control of external VGA and offset control seamlessly with analog quadrature modulators such as the Multiple chip synchronization interface ADL537x FMOD series from Analog Devices, Inc. A 3-wire High performance, low noise PLL clock multiplier interface provides for programming/readback of many internal Digital inverse sinc filter parameters. Full-scale output current can be programmed over 100-lead, exposed paddle TQFP a range of 10 mA to 30 mA. The devices are manufactured on an advanced 0.18 m CMOS process and operate on 1.8 V and APPLICATIONS 3.3 V supplies for a total power consumption of 1.0 W. They are Wireless infrastructure enclosed in a 100-lead thin quad flat package (TQFP). W-CDMA, CDMA2000, TD-SCDMA, WiMax, GSM, LTE PRODUCT HIGHLIGHTS Digital high or low IF synthesis Internal digital upconversion capability 1. Ultralow noise and intermodulation distortion (IMD) Transmit diversity enable high quality synthesis of wideband signals from Wideband communications: LMDS/MMDS, point-to-point baseband to high intermediate frequencies. 2. A proprietary DAC output switching technique enhances dynamic performance. 3. The current outputs are easily configured for various single-ended or differential circuit topologies. 4. CMOS data input interface with adjustable setup and hold. 5. Novel 2, 4, and 8 interpolator/coarse complex modulator allows carrier placement anywhere in DAC bandwidth. TYPICAL SIGNAL CHAIN QUADRATURE MODULATOR/ COMPLEX I AND Q MIXER/ AMPLIFIER LO DC DC DIGITAL INTERPOLATION FILTERS I DAC POST DAC FPGA/ASIC/DSP ANALOG FILTER Q DAC A AD9776A/AD9778A/AD9779A Figure 1. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20072017 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com 06452-114AD9776A/AD9778A/AD9779A Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Inverse Sinc Filter ....................................................................... 38 Applications ....................................................................................... 1 Sourcing the DAC Sample Clock ................................................. 39 General Description ......................................................................... 1 Direct Clocking .......................................................................... 39 Product Highlights ........................................................................... 1 Clock Multiplication .................................................................. 39 Typical Signal Chain......................................................................... 1 Driving the REFCLK Input ....................................................... 42 Revision History ............................................................................... 3 Full-Scale Current Generation ..................................................... 43 Functional Block Diagram .............................................................. 4 Internal Reference ...................................................................... 43 Specifications ..................................................................................... 5 Gain and Offset Correction .......................................................... 44 DC Specifications ......................................................................... 5 I/Q Channel Gain Matching ..................................................... 44 Digital Specifications ................................................................... 6 Auxiliary DAC Operation ......................................................... 44 Digital Input Data Timing Specifications ................................. 7 LO Feedthrough Compensation .............................................. 45 AC Specifications .......................................................................... 8 Results of Gain and Offset Correction .................................... 45 Absolute Maximum Ratings ............................................................ 9 Input Data Ports.............................................................................. 46 Thermal Resistance ...................................................................... 9 Single Port Mode ........................................................................ 46 ESD Caution .................................................................................. 9 Dual Port Mode .......................................................................... 46 Pin Configurations and Function Descriptions ......................... 10 Input Data Referenced to DATACLK ...................................... 46 Typical Performance Characteristics ........................................... 16 Input Data Referenced to REFCLK ......................................... 47 Terminology .................................................................................... 24 Optimizing the Data Input Timing.......................................... 48 Theory of Operation ...................................................................... 25 Device Synchronization ................................................................. 49 Differences Between AD9776/AD9778/ AD9779 and Synchronization Logic Overview ............................................. 49 AD9776A/AD9778A/AD9779A............................................... 25 Synchronizing Devices to a System Clock .............................. 50 3-Wire Interface .............................................................................. 26 Interrupt Request Operation .................................................... 50 General Operation of the Serial Interface ............................... 26 Power Dissipation ........................................................................... 51 Instruction Byte .......................................................................... 26 Power-Down and Sleep Modes................................................. 52 Serial Interface Port Pin Descriptions ..................................... 27 Evaluation Board Overview .......................................................... 53 MSB/LSB Transfers..................................................................... 27 Evaluation Board Operation ..................................................... 53 3-Wire Interface Register Map ...................................................... 28 Outline Dimensions ....................................................................... 55 Interpolation Filter Architecture .................................................. 33 Ordering Guide .......................................................................... 55 Interpolation Filter Bandwidth Limits .................................... 37 Rev. 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