Dual 12-/14-/16-Bit, 1 GSPS, Digital-to-Analog Converters AD9776/AD9778/AD9779 FEATURES GENERAL DESCRIPTION Low power: 1.0 W 1 GSPS, 600 mW 500 MSPS, The AD9776/AD9778/AD9779 are dual, 12-/14-/16-bit, high full operating conditions dynamic range, digital-to-analog converters (DACs) that pro- SFDR = 78 dBc to f = 100 MHz OUT vide a sample rate of 1 GSPS, permitting multicarrier generation Single carrier WCDMA ACLR = 79 dBc 80 MHz IF up to the Nyquist frequency. They include features optimized Analog output: adjustable 8.7 mA to 31.7 mA, for direct conversion transmit applications, including complex R = 25 to 50 L digital modulation, and gain and offset compensation. The DAC Novel 2, 4, and 8 interpolator/coarse complex modulator outputs are optimized to interface seamlessly with analog quad- allows carrier placement anywhere in DAC bandwidth rature modulators such as the AD8349. A serial peripheral interface Auxiliary DACs allow control of external VGA and offset control (SPI) provides for programming/readback of many internal Multiple chip synchronization interface parameters. Full-scale output current can be programmed over a High performance, low noise PLL clock multiplier range of 10 mA to 30 mA. The devices are manufactured on an Digital inverse sinc filter advanced 0.18 m CMOS process and operate on 1.8 V and 100-lead, exposed paddle TQFP package 3.3 V supplies for a total power consumption of 1.0 W. They are APPLICATIONS enclosed in 100-lead TQFP packages. Wireless infrastructure PRODUCT HIGHLIGHTS WCDMA, CDMA2000, TD-SCDMA, WiMax, GSM 1. Ultralow noise and intermodulation distortion (IMD) Digital high or low IF synthesis enable high quality synthesis of wideband signals from Internal digital upconversion capability baseband to high intermediate frequencies. Transmit diversity 2. A proprietary DAC output switching technique enhances Wideband communications: LMDS/MMDS, point-to-point dynamic performance. 3. The current outputs are easily configured for various single-ended or differential circuit topologies. 4. CMOS data input interface with adjustable set up and hold. 5. Novel 2, 4, and 8 interpolator/coarse complex modulator allows carrier placement anywhere in DAC bandwidth. TYPICAL SIGNAL CHAIN QUADRATURE MODULATOR/ COMPLEX I AND Q MIXER/ AMPLIFIER LO DC DC DIGITAL INTERPOLATION FILTERS I DAC POST DAC FPGA/ASIC/DSP ANALOG FILTER Q DAC A AD9779 Figure 1. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 20052007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 05361-114AD9776/AD9778/AD9779 TABLE OF CONTENTS Features .............................................................................................. 1 SPI Register Map ............................................................................ 27 Applications....................................................................................... 1 Interpolation Filter Architecture.................................................. 31 General Description ......................................................................... 1 Interpolation Filter Minimum and Maximum Bandwidth Specifications .............................................................................. 35 Product Highlights ........................................................................... 1 Driving the REFCLK Input....................................................... 35 Typical Signal Chain......................................................................... 1 Internal PLL Clock Multiplier/Clock Distribution................ 36 Revision History ............................................................................... 2 Full-Scale Current Generation ................................................. 38 Functional Block Diagram .............................................................. 3 Power Dissipation....................................................................... 39 Specifications..................................................................................... 4 Power-Down and Sleep Modes................................................. 41 DC Specifications ......................................................................... 4 Interleaved Data Mode .............................................................. 41 Digital Specifications ................................................................... 6 Timing Information................................................................... 41 Digital Input Data Timing Specifications ................................. 7 Synchronization of Input Data to DATACLK AC Specifications.......................................................................... 7 Output (Pin 37)........................................................................... 43 Absolute Maximum Ratings............................................................ 8 Synchronization of Input Data to the REFCLK Input (Pin 5 and Pin 6) with PLL Enabled or Disabled............................... 43 Thermal Resistance ...................................................................... 8 Evaluation Board Operation ......................................................... 46 ESD Caution.................................................................................. 8 Modifying the Evaluation Board to Use the AD8349 On- Pin Configurations and Function Descriptions ........................... 9 Board Quadrature Modulator................................................... 48 Typical Performance Characteristics ........................................... 15 Evaluation Board Schematics ................................................... 49 Terminology .................................................................................... 24 Outline Dimensions ....................................................................... 56 Theory of Operation ...................................................................... 25 Ordering Guide .......................................................................... 56 Serial Peripheral Interface ......................................................... 25 MSB/LSB Transfers..................................................................... 26 REVISION HISTORY Added Table 19, Renumbered Tables Sequentially .................... 41 3/07Rev. 0 to Rev. A Changes to Figure 92 and Figure 93............................................. 42 Changes to Features.......................................................................... 1 Changes to Figure 94...................................................................... 42 Changes to Applications .................................................................. 1 Added New Figure 95, Renumbered Figures Sequentially ....... 42 Changes to General Product Highlights........................................ 1 Changes to Synchronization of Input Data to the REFCLK Input Added Figure 1, Renumbered Figures Sequentially..................... 1 (Pin 5 and Pin 6) with PLL Enabled or Disabled Section ......... 43 Changes to Table 1............................................................................ 4 Added New Figure 96, Renumbered Figures Sequentially ....... 43 Changes to Table 2............................................................................ 5 Changes to Figure 106 ................................................................... 51 Changes to Table 3............................................................................ 5 Changes to Figure 53 and Figure 54............................................. 26 7/05Revision 0: Initial Version Changes to Table 12........................................................................ 29 Changes to Power Dissipation Section ........................................ 39 Rev. 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