Dual 12-/14-/16-Bit, LVDS Interface, 500 MSPS DACs Data Sheet AD9780/AD9781/AD9783 FEATURES GENERAL DESCRIPTION High dynamic range, dual DAC parts The AD9780/AD9781/AD9783 include pin-compatible, high Low noise and intermodulation distortion dynamic range, dual digital-to-analog converters (DACs) with Single carrier W-CDMA ACLR = 80 dBc at 61.44 MHz IF 12-/14-/16-bit resolutions, and sample rates of up to 500 MSPS. Innovative switching output stage permits usable outputs The devices include specific features for direct conversion transmit beyond Nyquist frequency applications, including gain and offset compensation, and they LVDS inputs with dual-port or optional interleaved single- interface seamlessly with analog quadrature modulators such as port operation the ADL5370. Differential analog current outputs are programmable from A proprietary, dynamic output architecture permits synthesis 8.6 mA to 31.7 mA full scale of analog outputs even above Nyquist by shifting energy away Auxiliary 10-bit current DACs with source/sink capability for from the fundamental and into the image frequency. external offset nulling Full programmability is provided through a serial peripheral Internal 1.2 V precision reference voltage source interface (SPI) port. Some pin-programmable features are also Operates from 1.8 V and 3.3 V supplies offered for those applications without a controller. 315 mW power dissipation Small footprint, RoHS compliant, 72-lead LFCSP PRODUCT HIGHLIGHTS APPLICATIONS 1. Low noise and intermodulation distortion (IMD) enable high quality synthesis of wideband signals. Wireless infrastructure 2. Proprietary switching output for enhanced dynamic W-CDMA, CDMA2000, TD-SCDMA, WiMAX performance. Wideband communications 3. Programmable current outputs and dual auxiliary DACs LMDS/MMDS, point-to-point provide flexibility and system enhancements. RF signal generators, arbitrary waveform generators FUNCTIONAL BLOCK DIAGRAM CLKP AD9783 DUAL LVDS DAC CLKN IOUT1P 16-BIT I DAC IOUT1N INTERFACE LOGIC IOUT2P 16-BIT LVDS Q DAC IOUT2N INTERFACE GAIN D 15:0 DAC V , V IA IB GAIN DAC AUX1P OFFSET INTERNAL DAC AUX1N SERIAL REFERENCE PERIPHERAL AND AUX2P OFFSET INTERFACE BIAS DAC AUX2N Figure 1. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20072017 Analog Devices, Inc. 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DEINTERLEAVING LOGIC SDO SDIO SCLK CSB REFIO RESET 06936-001AD9780/AD9781/AD9783 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 General Operation of the Serial Interface ............................... 19 Applications ....................................................................................... 1 Instruction Byte .......................................................................... 19 General Description ......................................................................... 1 MSB/LSB Transfers .................................................................... 20 Product Highlights ........................................................................... 1 Serial Interface Port Pin Descriptions ..................................... 20 Functional Block Diagram .............................................................. 1 SPI Register Map ............................................................................ 21 Table of Contents .............................................................................. 2 SPI Register Descriptions .............................................................. 22 Revision History ............................................................................... 2 SPI Port, RESET, and Pin Mode ............................................... 24 Specifications ..................................................................................... 3 Parallel Data Port Interface ........................................................... 25 DC Specifications ......................................................................... 3 Optimizing the Parallel Port Timing ....................................... 25 Digital Specifications ................................................................... 4 BIST Operation ........................................................................... 27 AC Specifications .......................................................................... 5 Driving the CLK Input .............................................................. 27 Absolute Maximum Ratings ............................................................ 6 Full-Scale Current Generation ................................................. 28 Thermal Resistance ...................................................................... 6 DAC Transfer Function ............................................................. 28 ESD Caution .................................................................................. 6 Analog Modes of Operation ..................................................... 28 Pin Configurations and Function Descriptions ........................... 7 Power Dissipation....................................................................... 30 Typical Performance Characteristics ........................................... 10 Outline Dimensions ....................................................................... 31 Terminology .................................................................................... 18 Ordering Guide .......................................................................... 31 Theory of Operation ...................................................................... 19 Serial Peripheral Interface ......................................................... 19 REVISION HISTORY 8/2017Rev. B to Rev. C 6/2008Rev. 0 to Rev. A Changes to Table 12 ........................................................................ 22 Changed Maximum Sample Rate to 500 MHz Throughout ....... 1 Changes to Table 3 ............................................................................. 4 6/2012Rev. A to Rev. B Changes to Building the Array Section ....................................... 25 Changes to Table 2 ............................................................................ 4 Changes to Determining the SMP Value Section ...................... 25 Changes to Pins 25, 26, 29, and 30 Description, Table 6 ............. 7 Added Evaluation Board Schematics Section ............................. 30 Changes to Pins 9 to 24, 31 to 42, 25, 26, 29, and 30 Description, Updated Outline Dimensions ....................................................... 35 Table 7 ................................................................................................ 8 Changes to Pins 25, 26, 29, and 30 Description, Table 7 ............. 9 11/2007Revision 0: Initial Version Changes to SEEK Bit Function Description, Table 12 ............... 22 Changes to Parallel Data Port Interface Section ......................... 25 Changed f from 600 MHz to 500 MHz .............................. 26 DACCLK Added BIST Operation Section .................................................... 27 Changes to Driving the CLK Input Section and Figure 59 ....... 27 Removed Evaluation Board Schematics Section ........................ 31 Updated Outline Dimensions ....................................................... 31 Changes to Ordering Guide .......................................................... 31 Rev. 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