Dual 12-/14-/16-Bit 800 MSPS DAC with Low Power 32-Bit Complex NCO Data Sheet AD9785/AD9787/AD9788 FEATURES GENERAL DESCRIPTION Analog output: adjustable 8.7 mA to 31.7 mA, The AD9785/AD9787/AD9788 are 12-bit, 14-bit, and 16-bit, R = 25 to 50 L high dynamic range TxDAC devices, respectively, that provide Low power, fine complex NCO allows carrier placement a sample rate of 800 MSPS, permitting multicarrier generation anywhere in DAC bandwidth while adding <300 mW power up to the Nyquist frequency. Features are included for optimizing Auxiliary DACs allow I and Q gain matching and offset control direct conversion transmit applications, including complex Includes programmable I and Q phase compensation digital modulation, as well as gain, phase, and offset compens- Internal digital upconversion capability ation. The DAC outputs are optimized to interface seamlessly Multiple chip synchronization interface with analog quadrature modulators, such as the ADL5375 High performance, low noise PLL clock multiplier family from Analog Devices, Inc. A serial peripheral interface Digital inverse sinc filter (SPI) provides for programming and readback of many internal 100-lead, exposed pad TQFP package parameters. Full-scale output current can be programmed over a range of 10 mA to 30 mA. The AD9785/AD9787/AD9788 APPLICATIONS family is manufactured on a 0.18 m CMOS process and operates Wireless infrastructure from 1.8 V and 3.3 V supplies. It is enclosed in a 100-lead TQFP W-CDMA, CDMA2000, TD-SCDMA, WiMAX, GSM package. Digital high or low IF synthesis PRODUCT HIGHLIGHTS Transmit diversity Wideband communications 1. Low noise and intermodulation distortion (IMD) enable LMDS/MMDS, point-to-point high quality synthesis of wideband signals from baseband to high intermediate frequencies. 2. Proprietary DAC output switching technique enhances dynamic performance. 3. CMOS data input interface with adjustable setup and hold. 4. Low power complex 32-bit numerically controlled oscillators (NCOs). TYPICAL SIGNAL CHAIN QUADRATURE MODULATOR/ COMPLEX I AND Q MIXER/ AMPLIFIER LO DC DC DIGITAL INTERPOLATION FILTERS I DAC POST DAC FPGA/ASIC/DSP ANALOG FILTER Q DAC A Figure 1. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20082018 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 07098-001AD9785/AD9787/AD9788 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Input Data RAM ......................................................................... 37 Applications ....................................................................................... 1 Digital Datapath ............................................................................. 38 General Description ......................................................................... 1 Interpolation Filters ................................................................... 38 Product Highlights ........................................................................... 1 Quadrature Modulator .............................................................. 40 Typical Signal Chain ......................................................................... 1 Numerically Controlled Oscillator .......................................... 40 Revision History ............................................................................... 2 Inverse Sinc Filter ....................................................................... 40 Specifications ..................................................................................... 3 Digital Amplitude and Offset Control .................................... 41 DC Specifications ......................................................................... 3 Digital Phase Correction ........................................................... 41 Digital Specifications ................................................................... 4 Device Synchronization ................................................................. 42 AC Specifications .......................................................................... 5 Synchronization Logic Overview ............................................. 42 Absolute Maximum Ratings ............................................................ 6 Synchronizing Devices to a System Clock .............................. 44 Thermal Resistance ...................................................................... 6 Synchronizing Multiple Devices to Each Other ..................... 45 ESD Caution .................................................................................. 6 Interrupt Request Operation .................................................... 46 Pin Configurations and Function Descriptions ........................... 7 Driving the REFCLK Input ........................................................... 47 Typical Performance Characteristics ........................................... 13 DAC REFCLK Configuration ................................................... 47 Terminology .................................................................................... 20 Analog Outputs............................................................................... 50 Theory of Operation ...................................................................... 21 Digital Amplitude Scaling ......................................................... 50 Serial Port Interface .................................................................... 21 Power Dissipation ........................................................................... 52 SPI Register Map ............................................................................. 24 AD9785/AD9787/AD9788 Evaluation Boards........................... 54 SPI Register Descriptions .......................................................... 25 Output Configuration ................................................................ 54 Input Data Ports .............................................................................. 33 Digital Picture of Evaluation Board ......................................... 54 Single-Port Mode ........................................................................ 33 Evaluation Board Software ........................................................ 55 Dual-Port Mode .......................................................................... 33 Evaluation Board Schematics ................................................... 56 Input Data Referenced to DATACLK ...................................... 33 Outline Dimensions ....................................................................... 62 Input Data Referenced to REFCLK .......................................... 35 Ordering Guide .......................................................................... 62 Optimizing the Data Input Timing .......................................... 36 REVISION HISTORY 5/2018Rev. B to Rev. C 2/2009Rev. 0 to Rev. A Change to Table 32 ......................................................................... 45 Added Settling Time, to Within 0.5 LSBs Parameter, Table 1 ... 3 Added REFCLK Frequency Range, PLL Enabled Parameter, 2/2016Rev. A to Rev. B Table 2 .................................................................................................4 Changes to SPI SDIOSerial Data I/O Section ....................... 23 Changed SPI CSB to SPI CS ....................................... Throughout Changes to Table 9 .......................................................................... 24 Changes to General Description Section ...................................... 1 Changes to Table 11 ....................................................................... 26 Changes to Figure 2 and Table 6 ..................................................... 7 Changes to Table 12 ....................................................................... 27 Changes to Figure 3 and Table 7 ..................................................... 9 Changes to Table 13 ....................................................................... 28 Changes to Figure 4 and Table 8 ................................................... 11 Changes to Table 22 ....................................................................... 32 Changes to Figure 52 ...................................................................... 36 Changes to Dual-Port Mode Section ........................................... 33 Updated Outline Dimensions ....................................................... 62 Changes to Input Data RAM Section .......................................... 37 Changes to Ordering Guide .......................................................... 62 Changes to Digital Amplitude and Offset Control Section ...... 41 Changes to Direct Clocking Section ............................................ 47 1/2008Revision 0: Initial Version Rev. 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