14-Bit, 2400 MSPS RF DAC with 4-Channel Signal Processing Data Sheet AD9789 The on-chip rate converter supports a wide range of baud rates FEATURES with a fixed DAC clock. The digital upconverter can place the DOCSIS 3.0 performance: 4 QAM carriers channels from 0 to 0.5 fDAC. This permits four contiguous ACLR over full band (47 MHz to 1 GHz) channels to be synthesized and placed anywhere from dc to f . DAC 75 dBc f = 200 MHz OUT 72 dBc f = 800 MHz (noise) The AD9789 includes a serial peripheral interface (SPI) for OUT 67 dBc f = 800 MHz (harmonics) device configuration and status register readback. The flexible OUT Unequalized MER = 42 dB digital interface can be configured for data bus widths of 4, 8, On chip and bypassable 16, and 32 bits. It can accept real or complex data. 4 QAM encoders with SRRC filters, 16 to 512 interpolation, The AD9789 operates from 1.5 V, 1.8 V, and 3.3 V supplies for rate converters, and modulators a total power consumption of 1.6 W. It is supplied in a 164-ball Flexible data interface: 4, 8, 16, or 32 bits wide with parity chip scale package ball grid array for lower thermal impedance Power: 1.6 W (I = 20 mA, f = 2.4 GHz, LVDS interface) FS DAC and reduced package parasitics. No special power sequencing Direct to RF synthesis support with f mix mode S is required. The clock receiver powers up muted to prevent Built-in self-test (BIST) support start-up noise. Input connectivity check PRODUCT HIGHLIGHTS Internal random number generator 1. Highly integrated and configurable QAM mappers, inter- APPLICATIONS polators, and upconverters for direct synthesis of one to Broadband communications systems four DOCSIS- or DVB-C-compatible channels in a block. CMTS/DVB 2. Low noise and intermodulation distortion (IMD) perfor- Cellular infrastructure mance enable high quality synthesis of signals up to 1 GHz. Point-to-point wireless 3. Flexible data interface supports LVDS for improved SFDR or CMOS input data for less demanding applications. GENERAL DESCRIPTION 4. Interface is configurable from 4-bit nibbles to 32-bit words The AD9789 is a flexible QAM encoder/interpolator/upconverter and can run at up to 150 MHz CMOS or 150 MHz LVDS combined with a high performance, 2400 MSPS, 14-bit RF digital- double data rate (DDR). to-analog converter (DAC). The flexible digital interface can 5. Manufactured on a CMOS process, the AD9789 uses a accept up to four channels of complex data. The QAM encoder proprietary switching technique that enhances dynamic supports constellation sizes of 16, 32, 64, 128, and 256 with performance. SRRC filter coefficients for all standards. FUNCTIONAL BLOCK DIAGRAM QAM/ CMOS FILTER/ DATA 0TO 15 NCO LVDS 32 INPUT RISE PINS QAM/ AND DATA FILTER/ 2PARITY RETIMER NCO 16 150MHz PINS 14-BIT DATA FORMATTER/ INTERPOLATOR LVDS/CMOS ASSEMBLER 2.4GSPS AND BPF DAC CMOS QAM/ + SCALARS DATA 16 TO 31 FILTER/ LVDS NCO FALL DCO SPI QAM/ IRQ RS DATA FILTER/ FS NCO Figure 1. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 2009-2019 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 07852-001AD9789 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 SPI Register Descriptions .......................................................... 29 Applications ....................................................................................... 1 Theory of Operation ...................................................................... 39 General Description ......................................................................... 1 Datapath Signal Processing ....................................................... 39 Product Highlights ........................................................................... 1 Digital Block Upconverter ........................................................ 43 Functional Block Diagram .............................................................. 1 Digital Interface Modes ............................................................. 45 Revision History ............................................................................... 2 Analog Modes of Operation ..................................................... 54 Detailed Functional Block Diagrams ............................................. 3 Analog Control Registers .......................................................... 55 Specif icat ions ..................................................................................... 4 Voltage Reference ....................................................................... 56 DC Specifications ......................................................................... 4 DAC Output Stages .................................................................... 56 Digital Specifications ................................................................... 5 Clocking the AD9789 ................................................................ 57 AC Specifications .......................................................................... 6 Mu Delay Controller .................................................................. 58 Absolute Maximum Ratings ............................................................ 8 Interrupt Requests ...................................................................... 61 Thermal Resistance ...................................................................... 8 Recommended Start-Up Sequence .......................................... 62 ESD Caution .................................................................................. 8 Customer BIST Modes ................................................................... 63 Pin Configurations and Function Descriptions ........................... 9 Using the Internal PRN Generator to Test QAM Output AC Performance ................................................................................ 63 Typical Performance Characteristics ........................................... 12 Using the Internal Built-In Self-Test (BIST) to Test for Digital Terminology .................................................................................... 22 Data Input Connectivity ............................................................. 63 Serial Control Port .......................................................................... 23 QAM Constellation Maps ............................................................. 65 Serial Control Port Pin Descriptions ....................................... 23 Channelizer Mode Pin Mapping for CMOS and LVDS ............ 68 General Operation of Serial Control Port ............................... 23 Outline Dimensions ....................................................................... 74 Instruction Word (16 Bits) ........................................................ 24 Ordering Guide .......................................................................... 74 MSB/LSB First Transfers ............................................................ 24 SPI Register Map ............................................................................. 27 REVISION HISTORY 4/2019Rev. A to Rev. B Parameter Added Adjusted DAC Update Rate Parameter ......... 6 Change to General Description Section ........................................ 1 Changes to Captions for Figure 42, Figure 44, Figure 46, Change to Digital 16x Tunable Band-Pass Filter Section .......... 44 Figure 49 .......................................................................................... 18 Change to Retimer Operation Section ........................................ 49 Changes to Digital 16x Tunable Band-Pass Filter Section, Third Change to Endnote 1, Table 79 ..................................................... 62 Paragraph ......................................................................................... 44 Changes to Retimer and Latency Look-Up Tables Section, 7/2011Rev. 0 to Rev. A Second Paragraph ........................................................................... 50 Change: DVB to DVB-C ............................................... Throughout Changes to Captions for Figure 122, Figure 124, Figure 125 ... 65 Changes to Table 2, DAC Clock Input (CLKP, CLKN): Added DAC Clock Rate Parameter ............................................................. 5 4/2009Revision 0: Initial Version Changes to Table 3, Dynamic Performance, DAC Update Rate Rev. B Page 2 of 76