Complete 10-Bit 18 MSPS a CCD Signal Processor AD9804 FEATURES FUNCTIONAL BLOCK DIAGRAM 18 MSPS Correlated Double Sampler (CDS) PBLK AVDD AVSS CLPOB 6 dB to 40 dB 10-Bit Variable Gain Amplifier (VGA) Low Noise Clamp Circuits DRVDD Preblanking Function CLP DRVSS 10-Bit 18 MSPS A/D Converter 6dB TO 40dB 3-Wire Serial Digital Interface 10 10-BIT 3 V Single Supply Operation CDS CCDIN VGA DOUT ADC Low Power CMOS 48-Lead LQFP Package CLP VR BANDGAP T REFERENCE APPLICATIONS VRB 10 CLPDM PC Cameras Digital Still Cameras INTERNAL VGA GAIN CML BIAS REGISTER DVDD DIGITAL INTERNAL AD9804 DVSS INTERFACE TIMING PRODUCT DESCRIPTION The AD9804 is a complete analog signal processor for CCD SL SCK SDATA SHP SHD DATACLK applications. It features an 18 MHz single-channel architecture designed to sample and condition the outputs of interlaced and progressive scan area CCD arrays. The AD9804s signal chain consists of an input clamp, correlated double sampler (CDS), digitally controlled VGA, black level clamp, and a 10-bit A/D converter. The internal VGA gain register is programmed through a 3-wire serial digital interface. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties Tel: 781/329-4700 World Wide Web Site: AD9804SPECIFICATIONS (T to T , AVDD = DVDD = 3.0 V, f = f = f = 18 MHz, unless otherwise noted.) ANALOG SPECIFICATIONS MIN MAX DATACLK SHP SHD Parameter Min Typ Max Unit TEMPERATURE RANGE Operating 20 +85 C Storage 65 +150 C POWER SUPPLY VOLTAGE Analog, Digital, Digital Driver 2.8 3.0 3.6 V POWER CONSUMPTION 85 mW MAXIMUM CLOCK RATE 18 MHz CORRELATED DOUBLE SAMPLER (CDS) 1 Allowable CCD Reset Transient 500 mV 1 Max Input Range before Saturation 1.0 V p-p 1 Max CCD Black Pixel Amplitude 100 mV VARIABLE GAIN AMPLIFIER (VGA) Gain Control Resolution 1024 Steps Gain Range (VGA Gain Curve Shown in Figure 5) Min Gain (Code 95) 4 6 8 dB Max Gain (Code 1023) 38 40 42 dB BLACK LEVEL CLAMP Clamp Level (At ADC Output) 32 LSB A/D CONVERTER Resolution 10 Bits No Missing Codes 10 Bits Guaranteed Full-Scale Input Voltage 2.0 V VOLTAGE REFERENCE Reference Top Voltage (VRT) 2.0 V Reference Bottom Voltage (VRB) 1.0 V NOTES 1 Input signal characteristics defined as follows: 500mV TYP RESET TRANSIENT 1V MAX 100mV MAX INPUT OPTICAL SIGNAL RANGE BLACK PIXEL Specifications subject to change without notice. DIGITAL SPECIFICATIONS (DRVDD = 2.7 V, C = 20 pF.) L Parameter Symbol Min Typ Max Unit LOGIC INPUTS High Level Input Voltage V 2.1 V IH Low Level Input Voltage V 0.6 V IL High Level Input Current I 10 A IH Low Level Input Current I 10 A IL Input Capacitance C 10 pF IN LOGIC OUTPUTS High Level Output Voltage V 2.1 V OH Low Level Output Voltage V 0.6 V OL High Level Output Current I 50 A OH Low Level Output Current I 50 A OL Specifications subject to change without notice. 2 REV. 0 OBSOLETE