Complete 16-Bit Imaging a Signal Processor AD9826 PRODUCT DESCRIPTION FEATURES The AD9826 is a complete analog signal processor for imaging 16-Bit 15 MSPS A/D Converter applications. It features a 3-channel architecture designed to 3-Channel 16-Bit Operation up to 15 MSPS sample and condition the outputs of trilinear color CCD arrays. 1-Channel 16-Bit Operation up to 12.5 MSPS Each channel consists of an input clamp, Correlated Double 2-Channel Mode for Mono Sensors with Odd/Even Outputs Sampler (CDS), offset DAC, and Programmable Gain Amplifier Correlated Double Sampling (PGA), multiplexed to a high-performance 16-bit A/D converter. 1~6 Programmable Gain 300 mV Programmable Offset The AD9826 can operate at speeds greater than 15 MSPS with Input Clamp Circuitry reduced performance. Internal Voltage Reference The CDS amplifiers may be disabled for use with sensors that Multiplexed Byte-Wide Output do not require CDS, such as Contact Image Sensors (CIS), Optional Single Byte Output Mode CMOS active pixel sensors, and Focal Plane Arrays. 3-Wire Serial Digital Interface 3 V/5 V Digital I/O Compatibility The 16-bit digital output is multiplexed into an 8-bit output word, 28-Lead SSOP Package which is accessed using two read cycles. There is an optional Low Power CMOS: 400 mW (Typ) single byte output mode. The internal registers are programmed Power-Down Mode Available through a 3-wire serial interface, and provide adjustment of the gain, offset, and operating mode. APPLICATIONS The AD9826 operates from a single 5 V power supply, typically Flatbed Document Scanners consumes 400 mW of power, and is packaged in a 28-lead SSOP. Digital Copier Multifunction Peripherals Infrared Imaging Applications Machine Vision FUNCTIONAL BLOCK DIAGRAM AVDD AVSS CML CAPT CAPB AVSS DRVDD DRVSS AVDD AD9826 VINR CDS PGA OEB BANDGAP 9-BIT REFERENCE DAC 16 16:8 8 3:1 16-BIT VING PGA DOUT CDS MUX MUX ADC 9-BIT DAC CONFIGURATION REGISTER MUX VINB CDS PGA REGISTER SCLK DIGITAL RED SLOAD 6 CONTROL 9-BIT GREEN INTERFACE DAC GAIN BLUE SDATA INPUT REGISTERS CLAMP RED 9 OFFSET BIAS GREEN OFFSET BLUE REGISTERS CDSCLK1 CDSCLK2 ADCCLK REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties that Tel: 781/329-4700 www.analog.com may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: Analog Devices, Inc., AD9826SPECIFICATIONS (T to T , AVDD = 5 V, DRVDD = 5 V, CDS Mode, f = 15 MHz, f = f = 5 MHz, PGA MIN MAX ADCCLK CDSCLK1 CDSCLK2 ANALOG SPECIFICATIONS Gain = 1, Input range = 4 V p-p, unless otherwise noted.) Parameter Min Typ Max Unit MAXIMUM CONVERSION RATE 3-Channel Mode with CDS 30 MSPS 2-Channel Mode with CDS 30 MSPS 1-Channel Mode with CDS 18 MSPS ACCURACY (ENTIRE SIGNAL PATH) ADC Resolution 16 Bits Integral Nonlinearity (INL) 16 LSB Differential Nonlinearity (DNL) 0.5 LSB No Missing Codes Guaranteed ANALOG INPUTS 1 Input Signal Range (Programmable) 2.0/4.0 V p-p 1 Allowable Reset Transient 1.0 V 2 Input Limits AVSS 0.3 AVDD + 0.3 V Input Capacitance 10 pF Input Bias Current 10 nA AMPLIFIERS PGA Gain 1 6 V/V 2 PGA Gain Resolution 64 Steps PGA Gain Monotonicity Guaranteed Programmable Offset 300 +300 mV Programmable Offset Resolution 512 Steps Programmable Offset Monotonicity Guaranteed NOISE AND CROSSTALK Total Output Noise PGA Minimum 3.0 LSB rms Total Output Noise PGA Maximum 9.0 LSB rms Channel-to-Channel Crosstalk 15 MSPS 70 dB 6 MSPS 90 dB POWER SUPPLY REJECTION AVDD = 5 V 0.25 V 0.1 % FSR DIFFERENTIAL VREF (at 25C) CAPTCAPB 2.0 V TEMPERATURE RANGE Operating 40 +85 C Storage 65 +150 C POWER SUPPLIES AVDD 4.75 5.0 5.25 V DRVDD 3.0 5.0 5.25 V OPERATING CURRENT AVDD 75 mA DRVDD 5 mA Power-Down Mode 200 A POWER DISSIPATION 3-Channel Mode 400 mW 1-Channel Mode 300 mW NOTES 1 Linear Input Signal Range is from 0 V to 4 V when the CCDs reference level is clamped to 4 V by the AD9826s input clamp. 4V SET BY INPUT CLAMP (3V OPTION ALSO AVAILABLE) 1V TYP 4V p-p MAX INPUT SIGNAL RANGE RESET TRANSIENT GND 6.0 2 Gain= The PGA Gain is approximately linear in dB and follows the equation: where G is the register value. 63 G 1+5.0 63 Specifications subject to change without notice. REV. B 2