Mixed-Signal Front-End (MxFE) Baseband Transceiver for Broadband Applications Data Sheet AD9861 FEATURES FUNCTIONAL BLOCK DIAGRAM Receive path includes dual 10-bit analog-to-digital converters VIN+A ADC with internal or external reference, 50 MSPS and 80 MSPS DATA Rx DATA VINA MUX versions AND VIN+B LATCH ADC Transmit path includes dual 10-bit, 200 MSPS digital-to-analog VINB I/O converters with 1, 2, or 4 interpolation and programmable INTERFACE I/O CONTROL gain control INTERFACE CONFIGURATION FLEXIBLE LOW-PASS Internal clock distribution block includes a programmable phase- BLOCK I/O BUS INTERPOLATION 0:19 FILTER locked loop and timing generation circuitry, allowing single- IOUT+A reference clock operation DATA DAC IOUTA LATCH 20-pin flexible I/O data interface allows various interleaved or AND IOUT+B DEMUX Tx DATA noninterleaved data transfers in half-duplex mode and DAC IOUTB interleaved data transfers in full-duplex mode Configurable through register programmability or optionally AUX ADC limited programmability through mode pins Independent Rx and Tx power-down control pins AUX DAC 64-lead LFCSP package (9 mm 9 mm footprint) ADC CLOCK CLKIN 3 configurable auxiliary converter pins AUX DAC DAC CLOCK PLL APPLICATIONS AUX Broadband access ADC Broadband LAN AD9861 Communications (modems) AUX DAC 03606-0-001 Figure 1. GENERAL DESCRIPTION The AD9861 is a member of the MxFE familya group of integrated In half-duplex systems, the interface supports 20-bit parallel converters for the communications market. The AD9861 integrates transfers or 10-bit interleaved transfers. In full-duplex systems, the interface supports an interleaved 10-bit ADC bus and an dual 10-bit analog-to-digital converters (ADC) and dual 10-bit digital-to-analog converters (TxDAC). Two speed grades are interleaved 10-bit TxDAC bus. The flexible I/O bus reduces pin available, -50 and -80. The -50 is optimized for ADC sampling of 50 count and, therefore, reduces the required package size on the MSPS and less, while the -80 is optimized for ADC sample rates AD9861 and the device to which it connects. between 50 MSPS and 80 MSPS. The dual TxDACs operate at speeds The AD9861 can use either mode pins or a serial program- up to 200 MHz and include a bypassable 2 or 4 interpolation mable interface (SPI) to configure the interface bus, operate the filter. Three auxiliary converters are also available to provide ADC in a low power mode, configure the TxDAC interpolation required system level control voltages or to monitor system signals. rate, and control ADC and TxDAC power-down. The SPI The AD9861 is optimized for high performance, low power, small provides more programmable options for both the TxDAC path form factor, and to provide a cost-effective solution for the (for example, coarse and fine gain control and offset control for broadband communication market. channel matching) and the ADC path (for example, the internal The AD9861 uses a single input clock pin (CLKIN) to generate all duty cycle stabilizer, and twos complement data format). system clocks. The ADC and TxDAC clocks are generated within a The AD9861 is packaged in a 64-lead LFCSP (low profile, fine timing generation block that provides user programmable options pitched, chip scale package). The 64-lead LFCSP footprint is such as divide circuits, PLL multipliers, and switches. only 9 mm 9 mm, and is less than 0.9 mm high, fitting into A flexible, bidirectional 20-bit I/O bus accommodates a variety of tightly spaced applications such as PCMCIA cards custom digital back ends or open market DSPs. Rev. A Page 1 of 51 AD9861 Data Sheet TABLE OF CONTENTS Features ....................................................................................................... 1 Typical Performance Characteristics .................................................... 10 Applications ................................................................................................ 1 Terminolog y ............................................................................................. 21 Functional Block Diagram ....................................................................... 1 Theory of Operation ............................................................................... 22 General Description .................................................................................. 1 System Block ........................................................................................ 22 TABLE OF CONTENTS ........................................................................... 2 Rx Path Block ...................................................................................... 22 Tx Path Specifications ............................................................................... 3 Tx Path Block ...................................................................................... 24 Rx Path Specifications ............................................................................... 4 Auxiliary Converters .......................................................................... 27 Power Specifications .................................................................................. 5 Digital Block ........................................................................................ 30 Programmable Registers .................................................................... 42 Digital Specifications ................................................................................. 5 Timing Specifications ................................................................................ 6 Clock Distribution Block ................................................................... 45 Absolute Maximum Ratings ..................................................................... 7 Outline Dimensions ................................................................................ 49 ESD Caution ........................................................................................... 7 Ordering Guide ................................................................................... 49 Pin Configuration and Pin Function Descriptions ............................... 8 REVISION HISTORY 4/2017Rev. 0 to Rev. A Changes to Figure 3 and Table 8 ..................................................... 8 Updated Outline Dimensions ....................................................... 44 Changes to Ordering Guide .......................................................... 44 11/2003Revision 0: Initial Version Rev. A Page 2 of 51