AD9865BCPZRL Analog Devices

Broadband Modem Mixed-Signal Front End AD9865 FEATURES FUNCTIONAL BLOCK DIAGRAM TM Low cost 3.3 V CMOS MxFE for broadband modems 10-bit D/A converter 2/4 interpolation filter 200 MSPS DAC update rate IOUT G+ AD9865 Integrated 23 dBm line driver with 19.5 dB gain control 2-4X IOUT N+ PWR DWN IAMP TxDAC IOUT N MODE 10-bit, 80 MSPS A/D converter IOUT G TXEN/SYNC 0 TO 12dB 0 TO 7.5dB 12 dB to +48 dB low noise RxPGA (< 3.0 nV/rtHz) TXCLK 10 CLKOUT 1 CLK Third order, programmable low-pass filter ADIO 9:4 / SYN. CLKOUT 2 Tx 5:0 Flexible digital data path interface M 2 CLK OSCIN MULTIPLIER XTAL Half- and full-duplex operation ADIO 3:0 / Rx 5:0 Backward-compatible with AD9975 and AD9875 10 Various power-down/reduction modes RX+ RXE/SYNC ADC 2-POLE 1-POLE LPF LPF RXCLK 80MSPS RX Internal clock multiplier (PLL) 6 AGC 5:0 0 TO 6dB 6 TO 18dB 6 TO 24dB 2 auxiliary programmable clock outputs = 1dB = 6dB = 6dB 4 REGISTER SPI CONTROL Available in 64-lead chip scale package or bare die APPLICATIONS Figure 1. Powerline networking VDSL and HPNA GENERAL DESCRIPTION or to an internal low distortion current amplifier. The current The AD9865 is a mixed-signal front end (MxFE) IC for amplifier (IAMP) can be configured as a current- or voltage- transceiver applications requiring Tx and Rx path functionality mode line driver (with two external npn transistors) capable of with data rates up to 80 MSPS. Its flexible digital interface, delivering in excess of 23 dBm peak signal power. Tx power can power saving modes, and high Tx-to-Rx isolation make it well be digitally controlled over a 19.5 dB range in 0.5 dB steps. suited for half- and full-duplex applications. The digital inter- face is extremely flexible allowing simple interfaces to digital The receive path consists of a programmable amplifier back ends that support half- or full-duplex data transfers, thus (RxPGA), a tunable low-pass filter (LPF), and a 10-bit ADC. often allowing the AD9865 to replace discrete ADC and DAC The low noise RxPGA has a programmable gain range of solutions. Power saving modes include the ability to reduce 12 dB to +48 dB in 1 dB steps. Its input referred noise is less power consumption of individual functional blocks, or to power than 3 nV/rtHz for gain settings beyond 36 dB. The receive path down unused blocks in half-duplex applications. A serial port LPF cutoff frequency can be set over a 15 MHz to 35 MHz interface (SPI) allows software programming of the various range or simply bypassed. The 10-bit ADC achieves excellent functional blocks. An on-chip PLL clock multiplier and dynamic performance over a 5 MSPS to 80 MSPS span. Both synthesizer provide all the required internal clocks, as well as the RxPGA and the ADC offer scalable power consumption two external clocks from a single crystal or clock source. allowing power/performance optimization. The Tx signal path consists of a bypassable 2/4 low-pass The AD9865 provides a highly integrated solution for many interpolation filter, a 10-bit TxDAC, and a line driver. The broadband modems. It is available in a space saving 64-pin chip transmit path signal bandwidth can be as high as 34 MHz at an scale package and is specified over the commercial (40C to input data rate of 80 MSPS. The TxDAC provides differential +85C) temperature range. current outputs that can be steered directly to an external load Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Specifications subject to change without notice. No license is granted by implication Tel: 781.329.4700 www.analog.com or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.326.8703 2004 Analog Devices, Inc. All rights reserved. IOUT P+ IOUT P 04493-0-001AD9865 TABLE OF CONTENTS Specifications..................................................................................... 3 TxDAC and IAMP Architecture .............................................. 28 Tx Path Specifications.................................................................. 3 Tx Programmable Gain Control .............................................. 30 Rx Path Specifications.................................................................. 4 TxDAC Output Operation........................................................ 30 Power Supply Specifications ....................................................... 5 IAMP Current-Mode Operation.............................................. 30 Digital Specifications ................................................................... 6 IAMP Voltage-Mode Operation .............................................. 31 Serial Port Timing Specifications............................................... 7 IAMP Current Consumption Considerations........................ 32 Half-Duplex Data Interface (ADIO Port) Timing Receive Path .................................................................................... 33 Specifications ................................................................................ 7 Rx Programmable Gain Amplifier........................................... 33 Full-Duplex Data Interface (Tx and Rx Port) Timing Low-Pass Filter ........................................................................... 34 Specifications ................................................................................ 8 Analog-to-Digital Converter (ADC)....................................... 35 Explanation of Test Levels........................................................... 8 AGC Timing Considerations.................................................... 36 Absolute Maximum Ratings............................................................ 9 Clock Synthesizer ........................................................................... 37 Thermal Characteristics .............................................................. 9 Power Control and Dissipation .................................................... 39 ESD Caution.................................................................................. 9 Power-Down ............................................................................... 39 Pin Configuration and Function Descriptions........................... 10 Half-Duplex Power Savings ...................................................... 39 Typical Performance Characteristics ........................................... 12 Power Reduction Options......................................................... 40 Rx Path Typical Performance Characteristics ........................ 12 Power Dissipation ...................................................................... 42 TxDAC Path Typical Performance Characteristics ............... 16 Mode Select upon Power-Up and Reset.................................. 42 IAMP Path Typical Performance Characteristics .................. 18 Analog and Digital Loop-Back Test Modes............................ 43 Serial Port ........................................................................................ 19 PCB Design Considerations.......................................................... 44 Register Map Description ......................................................... 21 Component Placement.............................................................. 44 Serial Port Interface (SPI) ......................................................... 21 Power Planes and Decoupling.................................................. 44 Digital Interface .............................................................................. 23 Ground Planes ............................................................................ 44 Half-Duplex Mode ..................................................................... 23 Signal Routing ............................................................................ 44 Full-Duplex Mode...................................................................... 24 Evaluation Board ............................................................................ 46 RxPGA Control .......................................................................... 25 Outline Dimensions ....................................................................... 47 TxPGA Control .......................................................................... 27 Ordering Guide .......................................................................... 47 Transmit Path.................................................................................. 28 Digital Interpolation Filters ...................................................... 28 REVISION HISTORY Change to TxDAC Output Operation section............................ 30 11/04Data Sheet Changed from Rev. 0 to Rev. A Insert equation................................................................................ 37 Changes to Specifications Tables.................................................... 3 Change to Figure 84 caption ......................................................... 42 Changes to Serial Table.................................................................. 19 Changes to Full Duplex Mode section......................................... 24 11/03Revision 0: Initial Version Change to TxDAC and IAMP Architecture section .................. 29 Rev. A Page 2 of 48