Dual Interface for
Flat Panel Displays
AD9882
FEATURES FUNCTIONAL BLOCK DIAGRAM
Analog Interface
140 MSPS Maximum Conversion Rate
AD9882
Programmable Analog Bandwidth
ANALOG INTERFACE
0.5 V to 1.0 V Analog Input Range REF REFBYPASS
500 ps p-p PLL Clock Jitter at 140 MSPS
R
8
OUT
CLAMP
R A/D
AIN
3.3 V Power Supply
Full Sync Processing
G
8 OUT
CLAMP A/D
Midscale Clamping G
AIN
4:2:2 Output Format Mode
8 B
OUT
B CLAMP A/D
Digital Interface AIN
8
DVI 1.0 Compatible Interface
DATACK R
OUT
SOGIN
SYNC
112 MHz Operation HSOUT
HSYNC
PROCESSING AND
8
CLOCK VSOUT
High Skew Tolerance of 1 Full Input Clock G
FILT OUT
GENERATION
SOGOUT
Sync Detect for Hot Plugging VSYNC
8
B
OUT
Supports High Bandwidth Digital Content Protection
SCL
APPLICATIONS
DATACK
SERIAL REGISTER AND
SDA
RGB Graphics Processing POWER MANAGEMENT
MUXES
HSOUT
LCD Monitors and Projectors A
0
Plasma Display Panels
VSOUT
Scan Converter
DIGITAL INTERFACE
Microdisplays
R
X0+
SOGOUT
R
8 OUT
R
X0
Digital TV
R
X1+
DVI G
8
OUT
DE
R RECEIVER
X1
R B
8 OUT
X2+
R
X2
DATACK
R
XC+
R
GENERAL DESCRIPTION XC
DE
R
TERM
The AD9882 offers designers the flexibility of an analog interface
HSYNC
DDCSCL
and Digital Visual Interface (DVI) receiver integrated on a single
DDCSDA
HDCP VSYNC
MCL
chip. Also included is support for High bandwidth Digital
MDA
Content Protection (HDCP).
Analog Interface
The AD9882 is a complete 8-bit 140 MSPS monolithic analog
interface optimized for capturing RGB graphics signals from
personal computers and workstations. Its 140 MSPS encode Digital Interface
rate capability and full power analog bandwidth of 300 MHz The AD9882 contains a DVI 1.0 compatible receiver and supports
supports resolutions up to SXGA (1280 1024 at 75 Hz). display resolutions up to SXGA (1280 1024 at 60 Hz). The
receiver features an intra-pair skew tolerance of up to one full
The analog interface includes a 140 MHz triple ADC with
clock cycle.
internal 1.25 V reference, a Phase Locked Loop (PLL), and
programmable gain, offset, and clamp control. The user provides With the inclusion of HDCP, displays may now receive encrypted
only a 3.3 V power supply, analog input, and Hsync. Three- video content. The AD9882 allows for authentication of a video
state CMOS outputs may be powered from 2.2 V to 3.3 V. receiver, decryption of encoded data at the receiver, and renew-
ability of that authentication during transmission as specified by
The AD9882s on-chip PLL generates a pixel clock from Hsync.
the HDCP v1.0 protocol.
Pixel clock output frequencies range from 12 MHz to 140 MHz.
PLL clock jitter is typically 500 ps p-p at 140 MSPS. The AD9882 Fabricated in an advanced CMOS process, the AD9882 is
also offers full sync processing for composite sync and Sync-on- provided in a space-saving 100-lead LQFP surface-mount plastic
Green (SOG) applications. package and is specified over the 0C to 70C temperature range.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
may result from its use. No license is granted by implication or otherwise
Tel: 781/329-4700 www.analog.com
under any patent or patent rights of Analog Devices. Trademarks and
Fax: 781/326-8703 2003 Analog Devices, Inc. All rights reserved.
registered trademarks are the property of their respective companies.AD9882SPECIFICATIONS
ANALOG INTERFACE
(V = 3.3 V, V = 3.3 V, ADC Clock = Maximum Conversion Rate, unless
D DD
ELECTRICAL CHARACTERISTICS
otherwise noted.)
Test AD9882KST-100 AD9882KST-140
Parameter Temp Level Min Typ Max Min Typ Max Unit
RESOLUTION 8 8 Bits
DC ACCURACY
Differential Nonlinearity 25 CI 0.5 +1.25/1.0 0.5 +1.35/1.0 LSB
Full VI +1.35/1.0 +1.45/1.0 LSB
Integral Nonlinearity 25 CI 0.5 1.85 0.5 2.0 LSB
Full VI 2.0 2.3 LSB
No Missing Codes Full VI Guaranteed Guaranteed
ANALOG INPUT
Input Voltage Range
Minimum Full VI 0.5 0.5 V p-p
Maximum Full VI 1.0 1.0 V p-p
Gain Tempco 25 CV 100 100 ppm/ C
Input Bias Current Full IV 1 1 mA
Input Full-Scale Matching Full VI 1.5 8.0 1.5 8.0 % FS
Offset Adjustment Range Full VI 46 49 56 46 49 56 % FS
REFERENCE OUTPUT
Output Voltage Full VI 1.20 1.25 1.32 1.20 1.25 1.32 V
Temperature Coefficient Full V 50 50 ppm/ C
1
SWITCHING PERFORMANCE
Maximum Conversion Rate Full VI 100 140 MSPS
Minimum Conversion Rate Full IV 10 10 MSPS
Data to Clock Skew Full IV 0.5 +2.0 0.5 +2.0 ns
Serial Port Timing
t Full VI 4.7 4.7 ms
BUFF
t Full VI 4.0 4.0 ms
STAH
t Full VI 0 0 ms
DHO
t Full VI 4.7 4.7 ms
DAL
t Full VI 4.0 4.0 ms
DAH
t Full VI 250 250 ns
DSU
t Full VI 4.7 4.7 ms
STASU
t Full VI 4.0 4.0 ms
STOSU
Hsync Input Frequency Full IV 15 110 15 110 kHz
Maximum PLL Clock Rate Full VI 100 140 MHz
Minimum PLL Clock Rate Full IV 12 12 MHz
2 2
PLL Jitter 25 CIV 500 700 500 700 ps p-p
2 2
Full IV 1000 1000 ps p-p
Sampling Phase Tempco Full IV 15 15 ps/ C
DIGITAL INPUTS
Input Voltage, High (V ) Full VI 2.6 2.6 V
IH
Input Voltage, Low (V ) Full VI 0.8 0.8 V
IL
Input Current, High (I ) Full IV 1.0 1.0 mA
IH
Input Current, Low (I ) Full IV +1.0 +1.0 mA
IL
Input Capacitance 25 CV 3 3 pF
1
DIGITAL OUTPUTS
Output Voltage, High (V ) Full IV V 0.1 V 0.1 V
OH DD DD
Output Voltage, Low (V ) Full IV 0.4 0.4 V
OL
Duty Cycle, DATACK Full IV 45 50 55 45 50 55 %
Output Coding Binary Binary
2
REV. A