Dual Interface for Flat Panel Display AD9887A FEATURES FUNCTIONAL BLOCK DIAGRAM Analog interface ANALOG INTERFACE REF REFIN REFOUT 170 MSPS maximum conversion rate R 8 OUTA Programmable analog bandwidth 8 R CLAMP A/D 8 R AIN OUTB 0.5 V to 1.0 V analog input range G 8 OUTA 8 500 ps p-p PLL clock jitter at 170 MSPS G CLAMP A/D G AIN 8 OUTB 3.3 V power supply B 8 OUTA 8 Full sync processing CLAMP B A/D AIN 8 Midscale clamping 2 DATACK HSYNC 4:2:2 output format mode VSYNC HSOUT COAST SYNC Digital interface CLAMP PROCESSING VSOUT DVI 1.0-compatible interface CKINV AND CLOCK GENERATION SOGOUT 8 CKEXT RED A 170 MHz operation (2 pixels/clock mode) FILT 8 S RED B CDT High skew tolerance of 1 full input clock SOGIN 8 GREEN A Sync detect for hot plugging SCL 8 SERIAL REGISTER Supports high bandwidth digital content protection GREEN B SDA AND A1 8 POWER MANAGEMENT BLUE A A0 8 APPLICATIONS BLUE B DIGITAL INTERFACE R 8 OUTA 2 RGB graphics processing 8 DATACK Rx0+ R 8 OUTB Rx0 LCD monitors and projectors HSOUT G 8 OUTA Rx1+ 8 Plasma display panels G 8 Rx1 OUTB VSOUT Scan converters Rx2+ B 8 OUTA SOGOUT Rx2 8 Microdisplays B 8 OUTB RxC+ DVI DE Digital TVs RxC 2 DATACK RECEIVER RTERM DE HSOUT GENERAL DESCRIPTION VSOUT DDCSCL The AD9887A offers an analog interface receiver and a digital DDCSDA visual interface (DVI) receiver integrated on a single chip, HDCP MCL MDA supports high bandwidth digital content protection (HDCP), AD9887A and is software and pin-to-pin compatible with the AD9887. Figure 1. Analog Interface Digital Interface The complete 8-bit, 170 MSPS, monolithic analog interface is The AD9887A contains a DVI 1.0-compatible receiver and optimized for capturing RGB graphics signals from personal supports resolutions up to 1600 1200 (UXGA) at 60 Hz. The computers and workstations. Its 170 MSPS encode rate capability receiver operates with true color (24-bit) panels in one or two and full-power analog bandwidth of 330 MHz support resolutions pixel(s) per clock mode and features an intrapair skew tolerance of up to 1600 1200 (UXGA) at 60 Hz. The interface includes of up to one full clock cycle. With the inclusion of HDCP, a 170 MHz triple ADC with internal 1.25 V reference a phase- displays can receive encrypted video content. The AD9887A locked loop (PLL) and programmable gain, offset, and clamp allows for authentication of a video receiver, decryption of encoded controls. The user provides only a 3.3 V power supply, analog data at the receiver, and renewability of authentication during input, and Hsync. Three-state CMOS outputs can be powered transmission, as specified by the HDCP v1.0 protocol. Fabricated from 2.5 V to 3.3 V. The analog interface also offers full sync in an advanced CMOS process, the AD9887A is provided in a processing for composite sync and sync-on-green (SOG) appli- 160-lead, surface-mount, plastic MQFP and is specified over the cations. The AD9887A on-chip PLL generates a pixel clock from 0C to 70C temperature range. The AD9887A is also available Hsync with output frequencies ranging from 12 MHz to 170 MHz. in an RoHS compliant package. PLL clock jitter is typically 500 ps p-p at 170 MSPS. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 20032007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. MUXES 02838-001AD9887A TABLE OF CONTENTS Features .............................................................................................. 1 Hot-Plug Detect.......................................................................... 27 Applications....................................................................................... 1 Power Management ................................................................... 27 General Description ......................................................................... 1 Scan Function ............................................................................. 28 Functional Block Diagram .............................................................. 1 Theory of OperationDigital Interface...................................... 29 Revision History ............................................................................... 2 Capturing Encoded Data........................................................... 29 Specifications..................................................................................... 3 Data Frames ................................................................................ 29 Analog Interface ........................................................................... 3 Special Characters ...................................................................... 29 Digital Interface ............................................................................ 5 Channel Resynchronization...................................................... 29 Absolute Maximum Ratings............................................................ 7 Data Decoder .............................................................................. 29 Explanation of Test Levels........................................................... 7 HDCP .......................................................................................... 29 ESD Caution.................................................................................. 7 General Timing DiagramsDigital Interface............................ 31 Pin Configuration and Function Descriptions............................. 8 Timing Mode DiagramsDigital Interface ........................... 31 Pin Function DetailsPins Shared Between Digital and 2-Wire Serial Register Map ........................................................... 32 Analog Interfaces........................................................................ 11 2-Wire Serial Control Register Details.................................... 35 Pin Function DetailsAnalog Interface ................................. 13 Theory of OperationSync Processing ...................................... 48 Pin Function DetailsDigital Interface.................................. 16 Sync Stripper............................................................................... 48 Theory of Operation and Design GuideAnalog Interface .... 17 Sync Separator ............................................................................ 48 General Description................................................................... 17 PCB Layout Recommendations.................................................... 49 Input Signal Handling................................................................ 17 Analog Interface Inputs............................................................. 49 HSYNC and VSYNC Inputs...................................................... 17 Digital Interface Inputs.............................................................. 49 Clamping ..................................................................................... 17 Power Supply Bypassing............................................................ 49 Gain and Offset Control............................................................ 18 PLL ............................................................................................... 50 Sync-on-Green Input ................................................................. 19 OutputsBoth Data and Clocks.............................................. 50 Clock Generation ....................................................................... 19 Digital Inputs .............................................................................. 50 Alternate Pixel Sampling Mode................................................ 22 Voltage Reference ....................................................................... 50 TimingAnalog Interface ........................................................ 23 Outline Dimensions ....................................................................... 51 Theory of OperationInterface Detection ................................ 27 Ordering Guide .......................................................................... 51 Active Interface Detection and Selection................................ 27 REVISION HISTORY Added TV Section in Table 7........................................................ 22 3/07Rev. A to Rev. B Deleted Digital Interface Pin List Table....................................... 24 Changes to Figure 1.......................................................................... 1 Changes to Theory of Operation Changes to Figure 28...................................................................... 27 (Interface Detection) Section........................................................ 28 Changes to Figure 37 and Figure 40............................................. 31 Added Hot-Plug Detect Section ................................................... 28 12/05Rev. 0 to Rev. A Changes to Table 8.......................................................................... 29 Changes to Figure 32...................................................................... 32 Updated Format..................................................................Universal Changes to Control Bits Section................................................... 44 Added Pb-Free Package .....................................................Universal Change to Figure 42 ....................................................................... 48 Changes to Figure 1.......................................................................... 1 Updated Outline Dimensions....................................................... 53 Changes to Specifications................................................................ 4 Changes to Ordering Guide .......................................................... 53 Changes to Table 4.......................................................................... 10 Deleted Analog Interface Pin List Table ...................................... 11 5/03Revision 0: Initial Version Added Figure 3................................................................................ 18 Rev. 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