100 MSPS/140 MSPS/170 MSPS Analog Flat Panel Interface Data Sheet AD9888 FEATURES FUNCTIONAL BLOCK DIAGRAM 170 MSPS maximum conversion rate 8 R 0 D A 8 AIN 2:1 R 7:0 500 MHz programmable analog bandwidth ADC CLAMP 8 MUX R 1 D B AIN R 7:0 0.5 V to 1.0 V analog input range 8 G 0 D A AIN 8 G 7:0 2:1 ADC CLAMP Less than 450 ps p-p PLL clock jitter at 170 MSPS 8 MUX G 1 D B AIN G 7:0 8 3.3 V power supply B 0 D A AIN 8 B 7:0 2:1 ADC CLAMP Full sync processing 8 MUX B 1 D B AIN B 7:0 2 Sync detect for hot plugging HSYNC0 DATACK 2:1 2:1 analog input mux MUX HSYNC1 HSOUT 4:2:2 output format mode VSYNC0 VSOUT 2:1 Midscale clamping MUX VSYNC1 SOGOUT Power-down mode SOGIN0 SYNC 2:1 PROCESSING Low power: <1 W typical at 170 MSPS MUX SOGIN1 AND CLOCK REF GENERATION REF APPLICATIONS COAST BYPASS CLAMP RGB graphics processing CKINV LCD monitors and projectors CKEXT Plasma display panels FILT Scan converters Microdisplays SCL SERIAL REGISTER SDA AND Digital TV AD9888 POWER MANAGEMENT A0 Figure 1. GENERAL DESCRIPTION The AD9888 is a complete 8-bit, 170 MSPS, monolithic analog range from 10 MHz to 170 MHz. PLL clock jitter is typically interface optimized for capturing RGB graphics signals from less than 450 ps p-p at 170 MSPS. When the COAST signal is personal computers and workstations. Its 170 MSPS encode rate presented, the PLL maintains its output frequency in the absence of capability and full-power analog bandwidth of 500 MHz supports HSYNC. A sampling phase adjustment is provided. Data, HSYNC, resolutions of up to 1600 1200 (UXGA) at 75 Hz. and clock output phase relationships are maintained. The PLL can be disabled, and an external clock input can be provided as For ease of design and to minimize cost, the AD9888 is a fully the pixel clock. The AD9888 also offers full sync processing for integrated interface solution for flat panel displays. The AD9888 composite sync and sync-on-green applications. includes an analog interface that has a 170 MHz triple ADC with an internal 1.25 V reference phase-locked loop (PLL) to generate a A CLAMP signal is generated internally or can be provided by the pixel clock from HSYNC and COAST midscale clamping and user through the CLAMP input pin. This device is fully program- programmable gain, offset, and clamp controls. The user provides mable via a 2-wire serial port. only a 3.3 V power supply, analog input, and HSYNC and COAST Fabricated in an advanced CMOS process, the AD9888 is signals. Three-state CMOS outputs can be powered from 2.5 V provided in a space-saving, 128-lead, MQFP, surface-mount, to 3.3 V. plastic package and is specified over the 0C to 70C temperature The on-chip PLL of the AD9888 generates a pixel clock from the range. The AD9888 is also available in a Pb-free package. HSYNC and COAST inputs. Pixel clock output frequencies Rev. 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Trademarks and registered trademarks are the property of their respective owners. 02442-001AD9888 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Chip Identification..................................................................... 24 Applications....................................................................................... 1 PLL Divider Control .................................................................. 24 Functional Block Diagram .............................................................. 1 Clock Generator Control .......................................................... 24 General Description ......................................................................... 1 Clamp Timing............................................................................. 24 Revision History ............................................................................... 3 HSYNC Pulse Width.................................................................. 25 Specifications..................................................................................... 4 Input Gain ................................................................................... 25 Absolute Maximum Ratings............................................................ 6 Input Offset ................................................................................. 25 Explanation of Test Levels........................................................... 6 Sync Control ............................................................................... 25 ESD Caution.................................................................................. 6 Input Control .............................................................................. 26 Pin Configuration and Function Descriptions............................. 7 Mode Control 1 .......................................................................... 29 Design Guide................................................................................... 12 2-Wire Serial Control Port ............................................................ 31 General Description................................................................... 12 Data Transfer via Serial Interface............................................. 31 Input Signal Handling................................................................ 12 Sync Processing .......................................................................... 32 Sync Processing Overview ........................................................ 12 Sync Slicer.................................................................................... 33 HSYNC and VSYNC Inputs...................................................... 12 Sync Separator ............................................................................ 33 Serial Control Port ..................................................................... 12 PCB Layout Recommendations.................................................... 34 Output Signal Handling............................................................. 12 Analog Interface Inputs............................................................. 34 Clamping ..................................................................................... 12 Power Supply Bypassing............................................................ 34 Gain and Offset Control............................................................ 13 PLL ............................................................................................... 34 Sync-on-Green Input ................................................................. 14 Outputs (Both Data and Clocks).............................................. 34 Clock Generation ....................................................................... 14 Digital Inputs .............................................................................. 35 Alternate Pixel Sampling Mode................................................ 16 Voltage Reference ....................................................................... 35 Timing.......................................................................................... 17 Outline Dimensions....................................................................... 36 2-Wire Serial Register Map ........................................................... 21 Ordering Guide .......................................................................... 36 2-Wire Serial Control Register Details ........................................ 24 Rev. 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