High Performance HDMI/DVI Transmitter Data Sheet AD9889B FEATURES FUNCTIONAL BLOCK DIAGRAM SCL SDA MCL MDA INT General HDMI /DVI transmitter compatible with HDMI v. 1.3, DVI v. 1.0, and HDCP v. 1.2 INTERRUPT HPD 2 HANDLER I C Single 1.8 V power supply SLAVE HDCP Video/audio inputs accept logic levels from 1.8 V to 3.3 V CORE 80-lead LQFP, Pb-free package HDCP-EDID MICRO- REGISTER 64-lead LFCSP, Pb-free package CONTROLLER CONFIGURATION LOGIC 76-ball CSP BGA, Pb-free package Digital video 2 DDCSDA I C MASTER 165 MHz operation supports all resolutions from 480i to DDCSCL CLK 1080p and UXGA at 60 Hz VSYNC VIDEO 80 MHz derivative supports all resolutions from 480i to COLOR Tx0/Tx0+ HSYNC DATA SPACE CAPTURE 1080i/720p and XGA at 70 Hz CONVER- DE Tx1/Tx1+ SION HDMI Programmable two-way color space converter 4:2:2 TO Tx D 23:0 4:4:4 CORE Tx2/Tx2+ Supports RGB, YCbCr, and DDR CONVER- SION Supports ITU656-based embedded syncs TxC/TxC+ XOR MASK Automatic input video format timing detection (CEA-861B) S/PDIF Digital audio MCLK Supports standard S/PDIF for stereo LPCM or compressed AUDIO 2 I S 3:0 DATA audio up to 192 kHz CAPTURE 2 LRCLK 8-channel, uncompressed, LPCM I S audio up to 192 kHz AD9889B SCLK Special features for easy system design 2 On-chip MPU with I C master to perform HDCP operations and EDID reading operations Figure 1. 2 5 V tolerant I C and HPD I/Os, no extra device needed No audio master clock needed for supporting S/PDIF 2 and I S 2 S audio. On-chip MPU reports HDMI events through interrupts and The AD9889B supports both S/PDIF and 8-channel I 2 registers Its high fidelity, 8-channel I S can transmit either stereo or 7.1 surround audio at 192 kHz. The S/PDIF can carry stereo LPCM APPLICATIONS audio or compressed audio, including DTS, THX, and Dolby DVD players and recorders Digital. Digital set-top boxes The AD9889B helps reduce system design complexity and cost A/V receivers by incorporating such features as an internal MPU for HDCP Digital cameras and camcorders 2 operations, an I C master for EDID reading, a single 1.8 V power HDMI repeater/splitter 2 supply, and 5 V tolerance on the I C and hot plug detect pins. GENERAL DESCRIPTION Fabricated in an advanced CMOS process, the AD9889B is The AD9889B is a 165 MHz, high definition multimedia inter- available in a space-saving, 76-ball CSP BGA or 64-lead LFCSP face (HDMI) v. 1.3 transmitter. It supports HDTV formats up to surface-mount package, and an 80-lead LQFP surface-mount 1080p, and computer graphic resolutions up to UXGA (1600 package. All packages are available as Pb-free and are specified 1200 at 60 Hz). With the inclusion of HDCP, the AD9889B allows from 25C to +85C. the secure transmission of protected content as specified by the HDCP v. 1.2 protocol. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20072014 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 06291-001AD9889B Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Applications Information .................................................................8 Applications ....................................................................................... 1 Design Resources ..........................................................................8 General Description ......................................................................... 1 Document Conventions ...............................................................8 Functional Block Diagram .............................................................. 1 PCB Layout Recommendations .......................................................9 Revision History ............................................................................... 2 Power Supply Bypassing ...............................................................9 Specif icat ions ..................................................................................... 3 Digital Inputs .................................................................................9 Absolute Maximum Ratings ............................................................ 4 External Swing Resistor ................................................................9 Explanation of Test Levels ........................................................... 4 Output Signals ...............................................................................9 ESD Caution .................................................................................. 4 Outline Dimensions ....................................................................... 10 Pin Configurations and Function Descriptions ........................... 5 Ordering Guide .......................................................................... 11 REVISION HISTORY 12/14Rev. A to Rev. B Changes to Features Section............................................................ 1 Changes to CLK Frequency Parameter, Table 1 ........................... 3 Updated Outline Dimensions ....................................................... 11 3/10Rev. 0 to Rev. A Changes to Clock Frequency Parameter, Table 1 ......................... 3 Changes to Digital Inputs Parameter, Table 2 ............................... 5 Changes to Table 3 ............................................................................ 7 Changes to Design Resources Section ........................................... 9 4/07Revision 0: Initial Version Rev. B Page 2 of 11