CCD Signal Processors with a Precision Timing Generator AD9891/AD9895 FEATURES PRODUCT DESCRIPTION AD9891: 10-Bit 20 MHz Version The AD9891 and AD9895 are highly integrated CCD signal AD9895: 12-Bit 30 MHz Version processors for digital still camera applications. Both include a Correlated Double Sampler (CDS) complete analog front end with A/D conversion combined with 4 6 dB Pixel Gain Amplifier (PxGA ) a full-function programmable timing generator. A Precision 2 dB to 36 dB 10-Bit Variable Gain Amplifier (VGA) Timing core allows adjustment of high speed clocks with 1 ns 10-Bit 20 MHz A/D Converter (AD9891) resolution at 20 MHz operation and 700 ps resolution at 30 12-Bit 30 MHz A/D Converter (AD9895) MHz operation. Black Level Clamp with Variable Level Control The AD9891 is specified at pixel rates of up to 20 MHz, and Complete On-Chip Timing Generator the AD9895 is specified at 30 MHz. The analog front end Precision Timing Core with 1 ns Resolution includes black level clamping, CDS, PxGA, VGA, and a 10-Bit On-Chip 5 V Horizontal and RG Drivers or 12-Bit A/D converter. The timing generator provides all the 2-Phase and 4-Phase H-Clock Modes necessary CCD clocks: RG, H-clocks, V-clocks, sensor gate 4-Phase Vertical Transfer Clocks pulses, substrate clock, and substrate bias control. Operation is Electronic and Mechanical Shutter Modes programmed using a 3-wire serial interface. On-Chip Driver for External Crystal Packaged in a space-saving 64-lead CSPBGA, the AD9891 and On-Chip Sync Generator with External Sync Option AD9895 are specified over an operating temperature range of 64-Lead CSPBGA Package 20C to +85C. APPLICATIONS Digital Still Cameras Digital Video Camcorders Industrial Imaging FUNCTIONAL BLOCK DIAGRAM VRT VRB AD9891/AD9895 4dB 6dB 2dB TO 36dB VREF 10 OR 12 CDS PxGA VGA ADC CCDIN DOUT CLAMP CLAMP DCLK INTERNAL CLOCKS CLPOB/PBLK RG FD/LD PRECISION HORIZONTAL TIMING MSHUT DRIVERS 4 GENERATOR H1H4 STROBE CLO 4 V1V4 V-H SYNC INTERNAL CONTROL GENERATOR 8 REGISTERS VSG1VSG8 VSUB SUBCK HD VD SYNC CLI SL SCK DATA PxGA is a registered trademark and Precision Timing is a trademark of Analog Devices, Inc. REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties that Tel: 781/329-4700 www.analog.com may result from its use. No license is granted by implication or otherwise Fax: 781/326-8703 Analog Devices, Inc., 2002 under any patent or patent rights of Analog Devices.AD9891/AD9895 TABLE OF CONTENTS SPECIFICATIONS . 3 Frame Transfer CCD Mode 24 DIGITAL SPECIFICATIONS . 3 Vertical Sensor Gate (Shift Gate) Timing .25 AD9891 ANALOG SPECIFICATIONS 4 SHUTTER TIMING CONTROL 26 AD9895 ANALOG SPECIFICATIONS 5 Normal Shutter Mode 26 TIMING SPECIFICATIONS 6 High Precision Shutter Mode .26 PACKAGE THERMAL CHARACTERISTICS 6 Low Speed Shutter Mode .26 ABSOLUTE MAXIMUM RATINGS . 6 SUBCK Suppression .26 ORDERING GUIDE 6 Readout After Exposure .27 PIN CONFIGURATION-AD9891 . 7 VSUB Control 27 PIN FUNCTION DESCRIPTIONS-AD9891 . 7 MSHUT and STROBE Control 27 PIN CONFIGURATION-AD9895 . 8 Example of Exposure and Readout of Interlaced Frame .29 PIN FUNCTION DESCRIPTIONS-AD9895 . 8 ANALOG FRONT END DESCRIPTION AND SPECIFICATION DEFINITIONS . 9 OPERATION . 30 EQUIVALENT CIRCUITS . 9 DC Restore . 30 TYPICAL PERFORMANCE CHARACTERISTICS 10 Correlated Double Sampler . 30 SYSTEM OVERVIEW 11 Input Clamp 30 Typical System Block Diagram 11 PxGA . 30 PRECISION TIMING HIGH SPEED TIMING PxGA Color Steering Mode Timing 31 GENERATION . 12 Variable Gain Amplifier 33 Timing Resolution .12 PxGA and VGA Gain Curves . 33 High Speed Clock Programmability 12 Optical Black Clamp 33 H-Driver and RG Outputs .13 A/D Converter . 33 Digital Data Outputs .13 POWER-UP AND SYNCHRONIZATION 34 HORIZONTAL CLAMPING AND BLANKING 15 Recommended Power-Up Sequence for Master Mode 34 Individual CLPOB, CLPDM, and PBLK Sequences .15 SYNC During Master Mode Operation .35 Individual HBLK Sequences .15 Synchronization in Slave Mode .35 Horizontal Sequence Control .15 POWER-DOWN MODE OPERATION 35 VERTICAL TIMING GENERATION 17 HORIZONTAL TIMING SEQUENCE EXAMPLE . 37 Individual Vertical Sequences 18 VERTICAL TIMING EXAMPLE . 39 Individual Vertical Regions 19 CIRCUIT LAYOUT INFORMATION 40 Complete Field: Combining the Regions 20 SERIAL INTERFACE TIMING .41 Vertical Sequence Alteration .21 Notes About Accessing a Double-Wide Register . 41 Second Vertical Sequence During VSG Lines 22 NOTES ON REGISTER LISTING 42 Vertical Sweep Mode Operation 22 COMPLETE REGISTER LISTING . 43 Vertical Multiplier Mode 24 OUTLINE DIMENSIONS . 57 REVISION HISTORY 57 2 REV. A