500 MSPS Direct Digital Synthesizer with 10-Bit DAC Data Sheet AD9911 FEATURES GENERAL DESCRIPTION Patented SpurKiller technology The AD9911 is a complete direct digital synthesizer (DDS). Multitone generation This device includes a high speed DAC with excellent wideband Test-tone modulation and narrowband spurious-free dynamic range (SFDR) as well as Up to 800 Mbps data throughput three auxiliary DDS cores without assigned digital-to-analog Matched latencies for frequency/phase/amplitude changes converters (DACs). These auxiliary channels are used for spur Linear frequency/phase/amplitude sweeping capability reduction, multitone generation, or test-tone modulation. Up to 16 levels of FSK, PSK, ASK The AD9911 is the first DDS to incorporate SpurKiller Programmable DAC full-scale current technology and multitone generation capability. Multitone 32-bit frequency tuning resolution mode enables the generation up to four concurrent carriers 14-bit phase offset resolution frequency, phase and amplitude can be independently 10-bit output amplitude-scaling resolution programmed. Multitone generation can be used for system Software-/hardware-controlled power-down tests, such as inter-modulation distortion and receiver blocker Multiple device synchronization sensitivity. SpurKilling enables customers to improve SFDR Selectable 4 to 20 REF CLK multiplier (PLL) performance by reducing the magnitude of harmonic Selectable REF CLK crystal oscillator components and/or the aliases of those harmonic components. 56-lead LFCSP Test-tone modulation efficiently enables sine wave modulation APPLICATIONS of amplitude on the output signal using one of the auxiliary Agile local oscillator DDS cores. Test and measurement equipment The AD9911 can perform modulation of frequency, phase, or Commercial and amateur radio exciter amplitude (FSK, PSK, ASK). Modulation is implemented by Radar and sonar storing profiles in the register bank and applying data to the Test-tone generation profile pins. In addition, the AD9911 supports linear sweep of Fast frequency hopping frequency, phase, or amplitude for applications such as radar Clock generation and instrumentation. (continued on Page 3) 500MSPS RECONSTRUCTED 10-BIT DAC DDS CORE SINE WAVE SPUR REDUCTION/ MODULATION CONTROL MULTITONE SYSTEM CLOCK SOURCE REF CLOCK TIMING AND INPUT CIRCUITRY CONTROL USER INTERFACE Figure 1. Basic Block Diagram Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20062016 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com 05785-002AD9911 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Linear Sweep No Dwell Mode .................................................. 25 Applications ....................................................................................... 1 Sweep and Phase Accumulator Clearing Functions .............. 26 General Description ......................................................................... 1 Output Amplitude Control ....................................................... 26 Revision History ............................................................................... 2 Synchronizing Multiple AD9911 Devices ................................... 28 Functional Block Diagram .............................................................. 3 Operation .................................................................................... 28 Specifications ..................................................................................... 4 Automatic Mode Synchronization ........................................... 28 Absolute Maximum Ratings ............................................................ 9 Manual Software Mode Synchronization ................................ 28 ESD Caution .................................................................................. 9 Manual Hardware Mode Synchronization .............................. 28 Equivalent Input and Output Circuits ....................................... 9 I/O Update, SYNC CLK, and System Clock Relationships 29 Pin Configuration and Function Descriptions ........................... 10 I/O Port ............................................................................................ 30 Typical Performance Characteristics ........................................... 12 Overview ..................................................................................... 30 Application Circuits ....................................................................... 17 Instruction Byte Description .................................................... 30 Theory of Operation ...................................................................... 18 I/O Port Pin Description ........................................................... 31 Primary DDS Core ..................................................................... 18 I/O Port Function Description ................................................. 31 SpurKiller/Multitone Mode and Test-Tone Modulation ....... 18 MSB/LSB Transfer Description ................................................ 31 D/A Converter ............................................................................ 18 I/O Modes of Operation ............................................................ 31 Modes of Operation ....................................................................... 19 Register Maps .................................................................................. 35 Single-Tone Mode ...................................................................... 19 Control Register Map ................................................................ 35 SpurKiller/Multitone Mode ...................................................... 19 Channel Register Map ............................................................... 36 Test-tone Mode ........................................................................... 20 Profile Register Map................................................................... 37 Reference Clock Modes ............................................................. 20 Control Register Descriptions ...................................................... 38 Scalable DAC Reference Current Control Mode ................... 21 Channel Select Register (CSR) ................................................. 38 Power-Down Functions ............................................................. 21 Channel Function Register (CFR) Description...................... 39 Shift Keying Modulation ........................................................... 21 Outline Dimensions ....................................................................... 41 Shift Keying Modulation Using SDIO Pins for RU/RD ........ 23 Ordering Guide .......................................................................... 41 Linear Sweep (Shaped) Modulation Mode ............................. 23 REVISION HISTORY 11/2016Rev. 0 to Rev. A Changes to Figure 43 Caption ....................................................... 25 Updated Outline Dimensions ....................................................... 41 5/2006Revision 0: Initial Version Rev. A Page 2 of 41