Low Power 250 MSPS 10-Bit DAC 1.8 V CMOS Direct Digital Synthesizer Data Sheet AD9913 FEATURES GENERAL DESCRIPTION 50 mW at up to 250 MSPS internal clock speed The AD9913 is a complete direct digital synthesizer (DDS) 100 MHz analog output designed to meet the stringent power consumption limits of Integrated 10-bit DAC portable, handheld, and battery-powered equipment. The 0.058 Hz or better frequency resolution AD9913 features a 10-bit digital-to-analog converter (DAC) 0.022 phase tuning resolution operating up to 250 MSPS. The AD9913 uses advanced DDS Programmable modulus in frequency equation technology, coupled with an internal high speed, high Phase noise 135 dBc per Hz 1 kHz offset (DAC output) performance DAC to form a complete, digitally-program- (<115 dBc per Hz when using on-board PLL multiplier) mable, high frequency synthesizer capable of generating a Excellent dynamic performance frequency agile analog output sinusoidal waveform at up to >80 dB SFDR 100 MHz (100 kHz offset) A OUT 100 MHz. Automatic linear frequency sweeping capability The AD9913 provides fast frequency hopping and fine tuning 8 frequency or phase offset profiles resolution. The AD9913 also offers fine resolution phase offset 1.8 V power supply control. Control words are loaded into the AD9913 through the Software and hardware controlled power-down serial or parallel I/O port. The AD9913 also supports a user- Parallel and serial programming options defined linear sweep mode of operation for generating highly 32-lead LFCSP package linearized swept waveforms of frequency. To support various Optional PLL REF CLK multiplier methods of generating a system clock, the AD9913 includes an Internal oscillator (can be driven by a single crystal) oscillator, allowing a simple crystal to be used as the frequency Phase modulation capability reference, as well as a high speed clock multiplier to convert the APPLICATIONS reference clock frequency up to the full system clock rate. For power saving considerations, many of the individual blocks of Portable and handheld equipment the AD9913 can be powered down when not in use. Agile LO frequency synthesis Programmable clock generator The AD9913 operates over the extended industrial temperature FM chirp source for radar and scanning systems range of 40C to +85C. FUNCTIONAL BLOCK DIAGRAM AD9913 10-BIT DDS DAC REF CLK INPUT TIMING AND CONTROL LOGIC CIRCUITRY USER INTERFACE Figure 1. Rev. E Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. Tel: 781.329.4700 20072020 Analog Devices, Inc. All rights reserved. No license is granted by implication or otherwise under any patent or patent rights of Analog Technical Support www.analog.com Devices. Trademarks and registered trademarks are the property of their respective owners. 07002-001AD9913 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Direct Switch Mode ................................................................... 14 Applications ...................................................................................... 1 Programmable Modulus Mode ................................................ 14 General Description ......................................................................... 1 Linear Sweep Mode .................................................................... 14 Functional Block Diagram .............................................................. 1 Clock Input (REF CLK) ............................................................... 18 Revision History ............................................................................... 2 REF CLK Overview ................................................................... 18 Specifications .................................................................................... 3 Crystal-Driven REF CLK ......................................................... 18 Electrical Specifications ............................................................... 3 Direct-Driven REF CLK .......................................................... 18 Absolute Maximum Ratings ........................................................... 5 CMOS-Driven REF CLK ......................................................... 18 ESD Caution.................................................................................. 5 Phase-Locked Loop (PLL) Multiplier ..................................... 18 Equivalent Circuits ....................................................................... 5 PLL Lock Indication .................................................................. 19 Pin Configuration and Function Descriptions ............................ 6 Power-Down Features ............................................................... 21 Typical Performance Characteristics ............................................. 8 I/O Programming ........................................................................... 22 Applications Circuits ..................................................................... 11 Serial Programming ................................................................... 22 Theory of Operation ...................................................................... 12 Parallel I/O Programming ........................................................ 23 DDS Core .................................................................................... 12 Register Update (I/O Update) .................................................. 25 Auxiliary Accumulator .............................................................. 13 Register Map and Bit Descriptions .............................................. 26 10-Bit DAC .................................................................................. 13 Register Map ............................................................................... 26 I/O Port ........................................................................................ 13 Register Bit Descriptions ........................................................... 28 Profile Selections ........................................................................ 13 Outline Dimensions ....................................................................... 32 Modes of Operation ....................................................................... 14 Ordering Guide .......................................................................... 32 Single Tone Mode ...................................................................... 14 REVISION HISTORY 11/2020Rev. D to Rev. E 6/2010Rev. 0 to Rev. A Changed CP-32-2 to CP-32-7 ...................................... Throughout Added Digital Input Voltage to Table 2 ......................................... 5 Changes to Figure 3 .......................................................................... 6 Added Exposed Pad Notation to Figure 3 and Table 3 ............... 5 Updated Outline Dimensions ....................................................... 32 Changes to Programmable Modulus Mode Section ................. 14 Changes to Ordering Guide .......................................................... 32 Changes to Serial Programming Section .................................... 22 Changes to Data Write Operation Section ................................. 24 3/2019Rev. C to Rev. D Added Register Update (I/O Update) section and Figure 35 .. 25 Change to DAC Control Register (0x02), Table 9 ..................... 26 Added Endnote 1 to Table 9 ......................................................... 26 Updated Outline Dimensions ....................................................... 32 Changes to Register Bit Descriptions Section and Bit 7 Description in Table 10 ................................................................. 28 11/2017Rev. B to Rev. C Changes to Table 15 and Table 16 ............................................... 31 Changed CP-32-7 to CP-32-2 ...................................... Throughout Added Exposed Pad Notation to Outline Dimensions ............. 32 Updated Outline Dimensions ....................................................... 32 Changes to Ordering Guide .......................................................... 32 10/2007Revision 0: Initial Version 8/2016Rev. A to Rev. B Changes to Table 7 ......................................................................... 20 Updated Outline Dimensions ....................................................... 32 Changes to Ordering Guide .......................................................... 32 Rev. E Page 2 of 32