Dual-Channel, 14-Bit CCD Signal Processor with Precision Timing Core AD9942 FEATURES GENERAL DESCRIPTION 40 MHz correlated double sampler (CDS) The AD9942 is a highly integrated dual-channel CCD signal 0 dB to 18 dB, 9-bit variable gain amplifier (VGA) processor for digital still camera applications. Each channel is 40 MSPS analog-to-digital converter (ADC) specified at pixel rates of up to 40 MHz. The AD9942 consists of Optical black clamp (CLPOB) with variable level control a complete analog front end with analog-to-digital conversion, Complete on-chip timing driver combined with a programmable timing driver. The Precision Precision Timing core with <550 ps resolution Timing core allows high speed clocks to be adjusted with On-chip 3 V horizontal and RG drivers 550 ps resolution. 4-phase H-clock mode The analog front end uses black level clamping and includes a 100-lead, 9 mm 9 mm, CSP BGA package VGA, a 40 MSPS ADC, and a CDS. The timing driver provides the high speed CCD clock drivers for RG A and RG B, as well APPLICATIONS as the H1A to H4A and H1B to H4B outputs. The 6-wire serial Signal processor for dual-channel CCD outputs interface is used to program the AD9942. Digital still cameras Digital video cameras Available in a space-saving, 9 mm 9 mm, CSP BGA package, High speed digital imaging applications the AD9942 is specified over an operating temperature range of 25C to +85C. FUNCTIONAL BLOCK DIAGRAM REFT A REFB A REFT B REFB B AD9942 VREF A VREF B 14 DOUT A CDS ADC CCDIN A VGA 0dB ~ 18dB CLAMP CLAMP 0dB ~ 18dB 14 DOUT B CDS VGA ADC CCDIN B INTERNAL CLOCKS RG A RG B PRECISION CLI A 4 HORIZONTAL TIMING H1A TO H4A DRIVERS CORE CLI B 4 H1B TO H4B SCK A SYNC INTERNAL GENERATOR REGISTERS SCK B HD A VD A HD B VD B SL A SDATA A SL B SDATA B Figure 1. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 05240-001AD9942 TABLE OF CONTENTS Features .............................................................................................. 1 High Speed Clock Programmability........................................ 19 Applications....................................................................................... 1 H Driver and RG Outputs......................................................... 21 General Description ......................................................................... 1 Digital Data Outputs.................................................................. 21 Functional Block Diagram .............................................................. 1 Channel A and Channel B Horizontal Clamping and Blanking ....22 Revision History ............................................................................... 2 Individual CLPOB and PBLK Sequences................................ 22 Specifications..................................................................................... 3 Individual HBLK Sequences..................................................... 22 General Specifications ................................................................. 3 Channel A and Channel B Special HBLK Patterns.................... 24 Digital Specifications ................................................................... 4 Horizontal Sequence Control ................................................... 24 Analog Specifications................................................................... 5 H-Counter Synchronization ..................................................... 25 Channel-to-Channel Specifications........................................... 6 Channel A and Channel B Power-Up Procedure....................... 26 Timing Specifications .................................................................. 7 Channel A and Channel B Analog Front End Operation......... 27 Absolute Maximum Ratings............................................................ 8 DC Restore .................................................................................. 27 Thermal Resistance ...................................................................... 8 Correlated Double Sampler ...................................................... 27 ESD Caution.................................................................................. 8 Channel A and Channel B Variable Gain Amplifier ............. 28 Pin Configuration and Function Descriptions............................. 9 Channel A and Channel B ADC .............................................. 28 Terminology .................................................................................... 11 Channel A and Channel B CLPOB.......................................... 28 Equivalent Input/Output Circuits ................................................ 12 Channel A and Channel B Digital Data Outputs................... 28 Typical Performance Characteristics ........................................... 13 Applications Information .............................................................. 29 System Overview ............................................................................ 14 Circuit Configuration ................................................................ 29 Serial Interface Timing .................................................................. 15 Grounding/Decoupling Recommendations ........................... 29 Complete Register Listing ......................................................... 16 Driving the CLI Input................................................................ 31 Channel A and Channel B Precision Timing............................... 19 Horizontal Timing Sequence Example.................................... 31 High Speed Timing Generation ............................................... 19 Outline Dimensions....................................................................... 33 Timing Resolution...................................................................... 19 Ordering Guide .......................................................................... 33 REVISION HISTORY 8/06Rev. 0 to Rev. A Changes to Table 3............................................................................ 5 Changes to Table 13........................................................................ 17 Change to Channel A and Channel B Variable Gain Amplifier Section............................................... 28 Updated Outline Dimensions ....................................................... 33 1/05Revision 0: Initial Version Rev. A Page 2 of 36