10-Bit CCD Signal Processor with Precision Timing Core AD9948 FEATURES GENERAL DESCRIPTION Correlated Double Sampler (CDS) The AD9948 is a highly integrated CCD signal processor for 0 dB to 18 dB Pixel Gain Amplifier (PxGA ) digital still camera applications. Specified at pixel rates of up to 6 dB to 42 dB 10-Bit Variable Gain Amplifier (VGA) 25 MHz, the AD9948 consists of a complete analog front end 10-Bit 25 MSPS A/D Converter with A/D conversion, combined with a programmable timing Black Level Clamp with Variable Level Control driver. The Precision Timing core allows adjustment of high Complete On-Chip Timing Driver speed clocks with 800 ps resolution. Precision Timing Core with 800 ps Resolution The analog front end includes black level clamping, CDS, PxGA, On-Chip 3 V Horizontal and RG Drivers VGA, and a 25 MHz 10-bit A/D converter. The timing driver 40-Lead LFCSP Package provides the high speed CCD clock drivers for RG and H1H4. Operation is programmed using a 3-wire serial interface. APPLICATIONS Digital Still Cameras Packaged in a space-saving 40-lead LFCSP package, the High Speed Digital Imaging Applications AD9948 is specified over an operating temperature range of 20C to +85C. FUNCTIONAL BLOCK DIAGRAM REFT REFB V REF 0dB TO 18dB 6dB TO 42dB 10 10-BIT DOUT CDS CCDIN PxGA VGA ADC CLAMP INTERNAL CLOCKS HBLK CLP/PBLK RG PRECISION HORIZONTAL TIMING CLI DRIVERS 4 CORE H1H4 SYNC INTERNAL GENERATOR REGISTERS AD9948 HD VD SL SCK SDATA REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. may result from its use. No license is granted by implication or otherwise Tel: 781/329-4700 www.analog.com under any patent or patent rights of Analog Devices. Trademarks and Fax: 781/326-8703 2003 Analog Devices, Inc. All rights reserved. registered trademarks are the property of their respective companies.AD9948SPECIFICATIONS GENERAL SPECIFICATIONS Parameter Min Typ Max Unit TEMPERATURE RANGE Operating 20 +85 C Storage 65 +150 C MAXIMUM CLOCK RATE 25 MHz POWER SUPPLY VOLTAGE AVDD, TCVDD (AFE, Timing Core) 2.7 3.0 3.6 V HVDD (H1H4 Drivers) 2.7 3.0 3.6 V RGVDD (RG Driver) 2.7 3.0 3.6 V DRVDD (D0D9 Drivers) 2.7 3.0 3.6 V DVDD (All Other Digital) 2.7 3.0 3.6 V POWER DISSIPATION 25 MHz, HVDD = RGVDD = 3 V, 100 pF H1H4 Loading* 220 mW Total Shutdown Mode 1 mW *The total power dissipated by the HVDD supply may be approximated using the equation Total HVDD Power=()C HVDD Pixel Frequency HVDD(Number of H Outputs Used) LOAD Reducing the H-loading, using only two of the outputs, and/or using a lower HVDD supply will reduce the power dissipation. Specifications subject to change without notice. DIGITAL SPECIFICATIONS (T to T , AVDD = DVDD = DRVDD = HVDD = RGVDD = 2.7 V, C = 20 pF, unless otherwise noted.) MIN MAX L Parameter Symbol Min Typ Max Unit LOGIC INPUTS High Level Input Voltage V 2.1 V IH Low Level Input Voltage V 0.6 V IL High Level Input Current I 10 A IH Low Level Input Current I 10 A IL Input Capacitance C 10 pF IN LOGIC OUTPUTS High Level Output Voltage, I = 2 mA V 2.2 V OH OH Low Level Output Voltage, I = 2 mA V 0.5 V OL OL CLI INPUT High Level Input Voltage (TCVDD/2 + 0.5 V) V 1.85 V IHCLI Low Level Input Voltage V 0.85 V ILCLI RG AND H-DRIVER OUTPUTS High Level Output Voltage (RGVDD 0.5 V and HVDD 0.5 V) V 2.2 V OH Low Level Output Voltage V 0.5 V OL Maximum Output Current (Programmable) 30 mA Maximum Load Capacitance 100 pF Specifications subject to change without notice. 2 REV. 0