AD9949KCPZ Analog Devices

12-Bit CCD Signal Processor with Precision Timing Core AD9949 FEATURES GENERAL DESCRIPTION New AD9949A supports CCD line length > 4096 pixels The AD9949 is a highly integrated CCD signal processor for Correlated double sampler (CDS) digital still camera applications. Specified at pixel rates of up to 0 dB to 18 dB pixel gain amplifier (PxGA) 36 MHz, the AD9949 consists of a complete analog front end 6 dB to 42 dB 10-bit variable gain amplifier (VGA) with A/D conversion, combined with a programmable timing 12-bit, 36 MSPS analog-to-digital converter (ADC) driver. The Precision Timing core allows adjustment of high Black level clamp with variable level control speed clocks with < 600 ps resolution. Complete on-chip timing driver The analog front end includes black level clamping, CDS, Precision Timing core with < 600 ps resolution PxGA, VGA, and a 36 MSPS, 12-bit ADC. The timing driver On-chip 3 V horizontal and RG drivers provides the high speed CCD clock drivers for RG and H1 to 40-lead LFCSP package H4. Operation is programmed using a 3-wire serial interface. APPLICATIONS Packaged in a space-saving, 40-lead LFCSP package, the Digital still cameras AD9949 is specified over an operating temperature range of High speed digital imaging applications 20C to +85C. FUNCTIONAL BLOCK DIAGRAM REFT REFB V REF 0dB TO 18dB 6dB TO 42dB 12 12-BIT DOUT CDS PxGA VGA CCDIN ADC CLAMP INTERNAL CLOCKS HBLK CLP/PBLK RG PRECISION HORIZONTAL TIMING CLI DRIVERS 4 CORE H1 TO H4 SYNC INTERNAL GENERATOR REGISTERS AD9949 HD VD SL SCK SDATA Figure 1. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Specifications subject to change without notice. No license is granted by implication Tel: 781.329.4700 www.analog.com or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.326.8703 2004 Analog Devices, Inc. All rights reserved. 03751-001AD9949 TABLE OF CONTENTS Specifications..................................................................................... 3 Individual HBLK Sequences..................................................... 21 General Specifications ................................................................. 3 Generating Special HBLK Patterns.............................................. 23 Digital Specifications ................................................................... 3 Horizontal Sequence Control ................................................... 23 Analog Specifications................................................................... 4 External HBLK Signal................................................................ 23 Timing Specifications .................................................................. 5 H-Counter Synchronization ..................................................... 24 Absolute Maximum Ratings............................................................ 6 Power-Up Procedure...................................................................... 25 Thermal Characteristics .............................................................. 6 Recommended Power-Up Sequence ....................................... 25 ESD Caution.................................................................................. 6 Analog Front End Description and Operation .......................... 26 Pin Configuration and Function Descriptions............................. 7 DC Restore .................................................................................. 26 Terminology ...................................................................................... 8 Correlated Double Sampler ...................................................... 26 Equivalent Input/Output Circuits .................................................. 9 PxGA............................................................................................ 26 Typical Performance Characteristics ........................................... 10 Variable Gain Amplifier ............................................................ 29 System Overview ............................................................................ 11 ADC ............................................................................................. 29 H-Counter Behavior .................................................................. 11 Optical Black Clamp .................................................................. 29 Serial Interface Timing .................................................................. 12 Digital Data Outputs.................................................................. 29 Complete Register Listing ............................................................. 13 Applications Information .............................................................. 30 Precision Timing High Speed Timing Generation...................... 18 Circuit Configuration ................................................................ 30 Timing Resolution...................................................................... 18 Grounding and Decoupling Recommendations.................... 30 High Speed Clock Programmability ........................................ 18 Driving the CLI Input................................................................ 31 H-Driver and RG Outputs ........................................................ 19 Horizontal Timing Sequence Example.................................... 31 Digital Data Outputs.................................................................. 19 Outline Dimensions....................................................................... 34 Horizontal Clamping and Blanking ............................................. 21 Ordering Guide .......................................................................... 34 Individual CLPOB and PBLK Sequences................................ 21 REVISION HISTORY 11/04Data Sheet Changed from Rev. A to Rev. B Changes to Table 12 ....................................................................... 17 Changes to Table 15 ....................................................................... 17 Changes to Ordering Guide .......................................................... 35 Changes to H-Counter Sync Section ........................................... 24 9/04Data Sheet Changed from Rev. 0 to Rev. A Changes to Recommended Power-Up Sequence Section......... 25 Changes to Features.......................................................................... 1 Changes to Ordering Guide .......................................................... 35 Changes to Analog Specifications .................................................. 4 5/03Revision 0: Initial Version Changes to Terminology Section.................................................... 9 Added H-Counter Behavior Section............................................ 12 Changes to Table 7.......................................................................... 14 Rev. B Page 2 of 36