AD9963BCPZ Analog Devices

10-/12-Bit, Low Power, Broadband MxFE Data Sheet AD9961/AD9963 FEATURES FUNCTIONAL BLOCK DIAGRAM Dual 10-bit/12-bit, 100 MSPS ADC TEMPERATURE AD9961/AD9963 SENSOR SNR = 67 dB, f = 30.1 MHz IN AUX AUXIN1 Dual 10-bit/12-bit, 170 MSPS DAC ADC ACLR = 74 dBc DLLFILT DLL AND AUX MUX AUXIO2 CLOCK DAC 5 channels of analog auxiliary input/output CLKP DISTRIBUTION AUX Low power, <425 mW at maximum sample rates CLKN AUXIO3 DAC Supports full and half-duplex data interfaces INTERNAL Small 72-lead LFCSP lead-free package TXCLK TXIP 12-BIT APPLICATIONS DAC TXIQ/TXnRX TXIN LPF 1/2/4/8 Wireless infrastructure TXQP TXD 11:0 12-BIT Picocell, femtocell basestations DAC DATA LPF TXQN ASSEMBLER 1/2/4/8 Medical instrumentation TRXCLK RXIP Ultrasound AFE 12-BIT TRXIQ ADC RXIN LPF Portable instrumentation 1/2 Signal generators, signal analyzers RXQP 12-BIT ADC RXQN TRXD 11:0 LPF GENERAL DESCRIPTION 1/2 AUX The AD9961/AD9963 are pin-compatible, 10-/12-bit, low DAC12A RESET DAC SERIAL power MxFE converters that provide two ADC channels with SDIO PORT AUX DAC12B SCLK LOGIC DAC sample rates of 100 MSPS and two DAC channels with sample CS rates to 170 MSPS. These converters are optimized for transmit REFERENCES LDO AND BIAS VREGs and receive signal paths of communication systems requiring low power and low cost. The digital interfaces provide flexible clocking options. The transmit is configurable for 1, 2, 4, and 8 interpolation. The receive path has a bypassable 2 decimating low-pass filter. Figure 1. PRODUCT HIGHLIGHTS The AD9961 and AD9963 have five auxiliary analog channels. 1. High Performance with Low Power Consumption. Three are inputs to a 12-bit ADC. Two of these inputs can be The DACs operate on a single 1.8 V to 3.3 V supply. configured as outputs by enabling 10-bit DACs. The other Transmit path power consumption is <100 mW at two channels are dedicated outputs from two independent 12-bit DACs. 170 MSPS. Receive path power consumption is <350 mW at 100 MSPS from 1.8 V supply. Sleep and power-down The high level of integrated functionality, small size, and low modes are provided for low power idle periods. power dissipation of the AD9961/AD9963 make them well- 2. High Integration. suited for portable and low power applications. The dual transmit and dual receive data converters, five channels of auxiliary data conversion and clock generation offer complete solutions for many modem designs. 3. Flexible Digital Interface. The interface mates seamlessly to most digital baseband processors. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. 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AUXADCREF REFIO TXCML RXCML RXBIAS LDO EN 08801-001AD9961/AD9963 Data Sheet TABLE OF CONTENTS Transmit DAC Outputs ............................................................. 42 Features .............................................................................................. 1 Device Clocking .............................................................................. 45 Applications ....................................................................................... 1 Clock Distribution ..................................................................... 45 General Description ......................................................................... 1 Driving the Clock Input ............................................................ 46 Functional Block Diagram .............................................................. 1 Clock Multiplication Using the DLL ....................................... 46 Product Highlights ........................................................................... 1 Configuring the Clock Doublers .............................................. 47 Revision History ............................................................................... 2 Digital Interfaces ............................................................................ 48 Specifications ..................................................................................... 3 TRx Port Operation (Full-Duplex Mode) ............................... 48 Absolute Maximum Ratings ............................................................ 8 Single ADC Mode ...................................................................... 48 Thermal Resistance ...................................................................... 8 Tx Port Operation (Full-Duplex Mode) ................................. 49 ESD Caution .................................................................................. 8 Half-Duplex Mode ..................................................................... 50 Pin Configurations and Function Descriptions ........................... 9 Auxiliary Converters ...................................................................... 52 Typical Performance Characteristics ........................................... 13 Auxiliary ADC ............................................................................ 52 Terminology .................................................................................... 18 Conversion Clock ....................................................................... 52 Theory of Operation ...................................................................... 19 Auxiliary DACs........................................................................... 53 Serial Control Port .......................................................................... 20 Power Supplies ................................................................................ 55 General Operation of Serial Control Port ............................... 20 Power Supply Configuration Examples ................................... 55 Sub Serial Interface Communications ..................................... 21 Power Dissipation....................................................................... 55 Configuration Registers ................................................................. 23 Example Start-Up Sequences ........................................................ 58 Configuration Register Bit Descriptions ................................. 24 Configuring the DLL ................................................................. 58 Receive Path..................................................................................... 35 Configuring the Clock Doublers (DDLL)............................... 58 Receive ADC Operation ............................................................ 35 Sensing temperature with the AUXADC ................................ 58 Decimation Filter and Digital Offset ....................................... 36 Outline Dimensions ....................................................................... 59 Transmit Path .................................................................................. 38 Ordering Guide .......................................................................... 59 Interpolation Filters.................................................................... 38 Transmit DAC Operation .......................................................... 40 REVISION HISTORY 8/12Rev. 0 to Rev. A Changes to Table 15 ........................................................................ 24 Changes to Figure 65 ...................................................................... 45 Added DLL Duty Cycle Caution Section .................................... 46 Changes to Table 22 ........................................................................ 47 Changes to Figure 93 and Power Supply Configuration Examples Section ............................................................................ 55 Added Example Start-Up Sequences Section ............................. 58 Updated Outline Dimensions ....................................................... 59 7/10Revision 0: Initial Version Rev. A Page 2 of 60