High Performance 8-Bit Display Interface AD9983A FEATURES FUNCTIONAL BLOCK DIAGRAM 8-bit analog-to-digital converters AD9983A 8 AUTO OFFSET 140 MSPS maximum conversion rate Low PLL clock jitter at 140 MSPS AUTO GAIN Pr/RED Automatic gain matching IN1 2:1 8 8-BIT CLAMP PGA Cb/Cr/RED OUT MUX ADC Pr/RED IN0 Automated offset adjustment 8 AUTO OFFSET 2:1 input mux AUTO GAIN Power-down via dedicated pin or serial register Y/GREEN 8 IN1 2:1 8-BIT 4:4:4, 4:2:2, and DDR output format modes CLAMP PGA Y/GREEN OUT MUX ADC Y/GREEN IN0 Variable output drive strength 8 AUTO OFFSET Odd/even field detection AUTO GAIN External clock input Pb/BLUE IN1 2:1 8 8-BIT CLAMP Cb/BLUE PGA OUT MUX ADC Regenerated Hsync output Pb/BLUE IN0 Programmable output high impedance control HSYNC1 2:1 Hsyncs per Vsync counter MUX HSYNC0 DATACK Pb-free package SOGOUT SYNC VSYNC0 2:1 PROCESSING MUX VSYNC1 O/E FIELD PLL APPLICATIONS HSOUT POWER SOGIN1 MANAGEMENT 2:1 Advanced TVs MUX VSOUT/A0 SOGIN0 Plasma display panels EXTCK/COAST CLAMP LCDTV REFHI FILT VOLTAGE REFS REFLO HDTV SDA SERIAL REGISTER SCL RGB graphics processing LCD monitors and projectors Figure 1. Scan converters GENERAL DESCRIPTION The AD9983A is a complete 8-bit, 140 MSPS, monolithic sampling clock phase adjustment is provided. Output data, analog interface optimized for capturing YPbPr video and RGB sync, and clock phase relationships are maintained. graphics signals. Its 140 MSPS encode rate capability and full The auto-offset feature can be enabled to automatically restore power analog bandwidth of 300 MHz support all HDTV video the signal reference levels and to automatically calibrate out any modes up to 1080i and 720p as well as graphics resolutions up offset differences between the three channels. The auto channel- to SXGA (1280 x 1024 at 75 Hz). to-channel gain matching feature can be enabled to minimize The AD9983A includes a 140 MHz triple ADC with an internal any gain mismatches between the three channels. reference, a PLL, and programmable gain, offset, and clamp The AD9983A also offers full sync processing for composite control. The user provides only a 1.8 V power supply and an sync and sync-on-green applications. A clamp signal is analog input. Three-state CMOS outputs can be powered from generated internally or may be provided by the user through the 1.8 V to 3.3 V. CLAMP input pin. The AD9983A on-chip PLL generates a sample clock from the Fabricated in an advanced CMOS process, the AD9983A is tri-level sync (for YPbPr video) or the horizontal sync (for RGB provided in a space-saving 80-lead, Pb-free, LQFP surface- graphics). Sample clock output frequencies range from 10 MHz mount plastic package, and is specified over the 0C to 70C to 140 MHz. With internal coast generation, the PLL maintains temperature range. its output frequency in the absence of sync input. A 32-step Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. OUTPUT DATA FORMATTER 06475-001AD9983A TABLE OF CONTENTS Features .............................................................................................. 1 Output Formatter ....................................................................... 20 Applications....................................................................................... 1 2-Wire Serial Control Port ............................................................ 21 Functional Block Diagram .............................................................. 1 Data Transfer via Serial Interface............................................. 21 General Description ......................................................................... 1 2-Wire Serial Register Map ........................................................... 23 Revision History ............................................................................... 2 2-Wire Serial Control Registers.................................................... 29 Specifications..................................................................................... 3 Chip Identification..................................................................... 29 Analog Interface Characteristics ................................................ 3 PLL Divider Control .................................................................. 29 Absolute Maximum Ratings............................................................ 5 Clock Generator Control .......................................................... 29 Explanation of Test Levels........................................................... 5 Phase Adjust................................................................................ 29 Thermal Resistance ...................................................................... 5 Input Gain ................................................................................... 30 ESD Caution.................................................................................. 5 Input Offset ................................................................................. 30 Pin Configuration and Function Descriptions............................. 6 Hsync Controls........................................................................... 30 Theory of Operation ...................................................................... 10 Vsync Controls ........................................................................... 31 Digital Inputs .............................................................................. 10 Coast and Clamp Controls........................................................ 32 Analog Input Signal Handling.................................................. 10 SOG Control ............................................................................... 33 Hsync and Vsync Inputs............................................................ 10 Input and Power Control........................................................... 34 Serial Control Port ..................................................................... 10 Output Control........................................................................... 35 Output Signal Handling............................................................. 10 Sync Processing .......................................................................... 36 Clamping ..................................................................................... 10 Detection Status.......................................................................... 36 Gain and Offset Control............................................................ 11 Polarity Status ............................................................................. 37 Sync-on-Green............................................................................ 12 Hsync Count ............................................................................... 37 Reference Bypassing................................................................... 12 Test Registers............................................................................... 37 Clock Generation ....................................................................... 13 PCB Layout Recommendations.................................................... 39 Sync Processing........................................................................... 15 Analog Interface Inputs............................................................. 39 Power Management.................................................................... 18 Outputs (Both Data and Clocks).............................................. 40 Timing Diagrams........................................................................ 18 Digital Inputs .............................................................................. 40 Hsync Timing ............................................................................. 19 Outline Dimensions....................................................................... 41 Coast Timing............................................................................... 20 Ordering Guide .......................................................................... 41 REVISION HISTORY 5/07Revision 0: Initial Version Rev. 0 Page 2 of 44