High Performance 10-Bit Display Interface AD9984A FEATURES FUNCTIONAL BLOCK DIAGRAM 10-bit, analog-to-digital converters AD9984A 10 AUTO OFFSET 170 MSPS maximum conversion rate AUTO GAIN Low PLL clock jitter at 170 MSPS Pr/RED 10 Automatic gain matching IN1 2:1 10-BIT Cb/Cr/RED CLAMP PGA OUT MUX ADC Pr/RED IN0 Automated offset adjustment 10 AUTO OFFSET 2:1 input mux AUTO GAIN Power-down via dedicated pin or serial register Y/GREEN 10 IN1 2:1 10-BIT CLAMP PGA Y/GREEN 4:4:4, 4:2:2, and DDR output format modes MUX OUT ADC Y/GREEN IN0 Variable output drive strength 10 AUTO OFFSET Odd/even field detection AUTO GAIN External clock input Pb/BLUE IN1 2:1 10 10-BIT CLAMP PGA Cb/BLUE OUT MUX ADC Pb/BLUE Regenerated Hsync output IN0 Programmable output high impedance control HSYNC1 2:1 Hsyncs per Vsync counter MUX HSYNC0 DATACK Sync-on-green (SOG) pulse filter SOGOUT VSYNC0 SYNC 2:1 PROCESSING Pb-free package MUX VSYNC1 ODD/EVEN FIELD PLL HSOUT POWER APPLICATIONS SOGIN1 2:1 MANAGEMENT MUX VSOUT/A0 SOGIN0 Advanced TVs EXTCK/COAST CLAMP Plasma display panels REFHI FILT VOLTAGE LCDTV REFS REFLO SDA SERIAL REGISTER HDTV SCL RGB graphics processing Figure 1. LCD monitors and projectors Scan converters GENERAL DESCRIPTION The AD9984A is a complete 10-bit, 170 MSPS, monolithic sampling clock phase adjustment is provided. Output data, analog interface optimized for capturing YPbPr video and RGB sync, and clock phase relationships are maintained. graphics signals. Its 170 MSPS encode rate capability and full The auto-offset feature can be enabled to automatically restore power analog bandwidth of 300 MHz support all HDTV video the signal reference levels and calibrate out any offset differences modes up to 1080p, as well as graphics resolutions up to UXGA between the three channels. The auto channel-to-channel gain- (1600 1200 at 60 Hz). matching feature can be enabled to minimize any gain The AD9984A includes a 170 MHz triple ADC with an internal mismatches between the three channels. reference, a PLL, and programmable gain, offset, and clamp The AD9984A also offers full sync processing for composite sync control. The user provides only a 1.8 V power supply and an and sync-on-green applications. A clamp signal is generated analog input. Three-state CMOS outputs can be powered from internally or can be provided by the user through the CLAMP 1.8 V to 3.3 V. input pin. The AD9984A on-chip PLL generates a sample clock from the Fabricated in an advanced CMOS process, the AD9984A is tri-level sync (for YPbPr video) or the horizontal sync (for RGB provided in a space-saving, Pb-free, 80-lead low profile quad graphics). Sample clock output frequencies range from 10 MHz flat package (LQFP) or 64-lead lead frame chip scale package to 170 MHz. With internal coast generation, the PLL maintains (LFCSP) and is specified over the 0C to 70C temperature range. its output frequency in the absence of a sync input. A 32-step Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. Tel: 781.329.4700 www.analog.com No license is granted by implication or otherwise under any patent or patent rights of Analog Fax: 781.461.3113 20072020 Analog Devices, Inc. All rights reserved. Devices. Trademarks and registered trademarks are the property of their respective owners. OUTPUT DATA FORMATTER 06476-001AD9984A TABLE OF CONTENTS Features .............................................................................................. 1 Output Formatter ....................................................................... 21 Applications ...................................................................................... 1 2-Wire Serial Control Port ............................................................ 22 Functional Block Diagram .............................................................. 1 Data Transfer via Serial Interface ............................................ 22 General Description ......................................................................... 1 2-Wire Serial Register Map ........................................................... 24 Revision History ............................................................................... 2 2-Wire Serial Control Registers ................................................... 30 Specifications .................................................................................... 3 Chip Identification ..................................................................... 30 Analog Interface Characteristics ................................................ 3 PLL Divider Control .................................................................. 30 Absolute Maximum Ratings ........................................................... 5 Clock Generator Control .......................................................... 30 Explanation of Test Levels .......................................................... 5 Phase Adjust ............................................................................... 30 Thermal Resistance ...................................................................... 5 Input Gain ................................................................................... 30 ESD Caution.................................................................................. 5 Input Offset ................................................................................. 31 Pin Configurations and Function Descriptions ........................... 6 Hsync Control ............................................................................ 31 Theory of Operation ...................................................................... 11 Vsync Control ............................................................................. 32 Digital Inputs .............................................................................. 11 Coast and Clamp Controls ....................................................... 33 Analog Input Signal Handling ................................................. 11 SOG Control ............................................................................... 34 Hsync and Vsync Inputs ........................................................... 11 Input and Power Control .......................................................... 35 Serial Control Port ..................................................................... 11 Output Control ........................................................................... 35 Output Signal Handling ............................................................ 11 Sync Processing .......................................................................... 36 Clamping ..................................................................................... 11 Detection Status .......................................................................... 37 Gain and Offset Control ............................................................ 12 Polarity Status ............................................................................. 37 Sync-on-Green ............................................................................ 13 Hsync Count ............................................................................... 38 Reference Bypassing ................................................................... 13 Test Registers .............................................................................. 38 Clock Generation ....................................................................... 14 PCB Layout Recommendations ................................................... 40 Sync Processing .......................................................................... 16 Analog Interface Inputs............................................................. 40 Power Management ................................................................... 19 Outputs (Both Data and Clocks) ............................................. 40 Timing Diagrams ....................................................................... 19 Digital Inputs .............................................................................. 41 Hsync Timing ............................................................................. 20 Outline Dimensions ....................................................................... 42 Coast Timing .............................................................................. 21 Ordering Guide .......................................................................... 42 REVISION HISTORY 11/2020Rev. 0 to Rev. A Changed CP-64-1 to CP-64-21 .................................... Throughout Changes to Figure 3 .......................................................................... 6 Updated Outline Dimensions ....................................................... 42 Changes to Ordering Guide .......................................................... 42 7/2007Revision 0: Initial Version Rev. A Page 2 of 44