Data Sheet AD9988 4T4R Direct RF Receiver and Transmitter FEATURES APPLICATIONS Flexible, reconfigurable radio common platform design Wireless communications infrastructure Transmitter/receiver channel bandwidth up to 1.2 GHz (4T4R) W-CDMA, LTE, LTE-A, massive multiple input multiple output (MIMO) RF DAC/RF ADC RF frequency range up to 7.5 GHz Point to point microwave, E-band, and 5G mmWave On-chip PLL with multichip synchronization Broadband communications systems External RF clock input option DOCSIS 3.0+ cable modem termination system (CMTS) Versatile digital features Communication test and measurement systems Selectable interpolation and decimation filters Configurable DDCs and DUCs GENERAL DESCRIPTION 8 fine complex DUCs (FDUC) and 4 coarse complex DUCs (CDUC) The AD9988 is a highly integrated device with four 16-bit, 12 8 fine complex DDCs (FDDC) and 4 coarse complex DDCs GSPS maximum sample rate, RF digital-to-analog converter (DAC) (CDDC) cores, and four 12-bit, 4 GSPS rate, RF analog-to-digital converter (ADC) cores. The device supports four transmitter channels and FDUCs and FDDCs are fully bypassable four receiver channels with a 4T4R configuration. This product is 2 independent 48-bit NCOs per DUC or DDC well suited for four-antenna TDD transmitter applications, where Programmable 192-tap PFIR filter for receive equalization the receiver path can be shared between receiver and observation Supports 4 different profile settings loaded via GPIO modes. The GPIO pins can be configured and toggled to support Receive AGC support different user modes, while phase coherency is maintained. The Fast detect with low latency for fast AGC control maximum radio channel bandwidth supported is 1.2 GHz in a 4T4R configuration and a sample resolution of 16 bits. The AD9988 Signal monitor for slow AGC control features a 16-lane 24.75 Gbps JESD204C or 15.5 Gbps JESD204B Dedicated AGC support pins serial data port that allows up to eight lanes per transmit/receive Transmit DPD support link, an on-chip clock multiplier, and digital signal processing capa- Programmable delay and gain per transmit data path bility targeted at multiband direct to RF radio applications. Coarse DDC delay adjust for DPD observation path Supports real or complex digital data (8-, 12-, or 16-bit) Auxiliary features ADC clock driver with selectable divide ratios Power amplifier downstream protection circuitry On-chip temperature monitoring unit Programmable GPIO pins support toggling between modes TDD power savings option and sharing ADCs SERDES JESD204B or JESD204C interface, 16 lanes up to 24.75 Gbps 8 lanes JESD204B/C transmitter (JTx) and 8 lanes JESD204B/C receiver (JRx) Supports Subclass 1 Supports multidevice synchronization 15 mm 15 mm, 324-ball BGA with 0.8 mm pitch Rev. A Information furnished by Analog Devices is believed to be accurate and reliableas i. However, no responsibility is assumed by Analog DOCUMENT FEEDBACK Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and TECHNICAL SUPPORT registered trademarks are the property of their respective owners.Data Sheet AD9988 TABLE OF CONTENTS Features................................................................ 1 CMOS Pin Specifications................................. 14 Applications........................................................... 1 DAC AC Specifications.....................................14 General Description...............................................1 ADC AC Specifications.....................................16 Functional Block Diagram......................................3 Timing Specifications....................................... 18 Specifications........................................................ 4 Absolute Maximum Ratings.................................20 Recommended Operating Conditions................ 4 Thermal Resistance......................................... 20 Power Consumption...........................................4 ESD Caution.....................................................20 DAC DC Specifications...................................... 5 Pin Configuration and Function Descriptions...... 21 ADC DC Specifications...................................... 6 Typical Performance Characteristics...................26 Clock Inputs and Outputs...................................7 DAC..................................................................26 Clock Input and Phase-Locked Loop (PLL) ADC..................................................................31 Frequency Specifications................................. 7 Theory of Operation.............................................38 DAC Sample Rate Specifications.......................7 Applications Information...................................... 39 ADC Sample Rate Specifications.......................9 Outline Dimensions............................................. 40 Input Data Rates Specifications....................... 10 Ordering Guide.................................................40 NCO Frequency Specifications........................ 11 Evaluation Boards............................................ 40 JESD204B and JESD204C Interface Electrical and Speed Specifications............... 11 REVISION HISTORY 7/2021Rev. 0 to Rev. A Changes to Table 20 .....................................................................................................................................20 3/2021Revision 0: Initial Version analog.com Rev. A 2 of 40