Integrated Mixed-Signal Front End (MxFE) Data Sheet AD9993 FEATURES GENERAL DESCRIPTION Quad 14-bit 250 MSPS ADC The AD9993 is a mixed-signal front-end (MxFE) device that SFDR = 83 dBc at 87 MHz input integrates four 14-bit ADCs and two 14-bit DACs. Figure 1 Dual 14-bit 500 MSPS DAC shows the block diagram of the MxFE. The MxFE is SFDR = 75 dBc at 20 MHz output programmable using registers accessed via a serial peripheral On-chip PLL clock synthesizer interface (SPI). ADC and DAC datapaths include FIFO buffers Low power to absorb phase differences between LVDS lane clocks and the 1536 mW, 1 GHz master clock, on-chip synthesizer data converter sampling clocks. 500 MHz double data rate (DDR) The MxFE DACs are part of the Analog Devices, Inc., high LVDS interfaces for DACs and ADCs speed CMOS DAC core family. These DACs are designed to be Small 12 mm 12 mm lead-free BGA package used in wide bandwidth communication system transmitter APPLICATIONS (Tx) signal chains. Point to point microwave backhaul radios The MxFE ADCs are multistage pipelined CMOS ADC cores Wireless repeaters designed for use in communications receivers. FUNCTIONAL BLOCK DIAGRAM DOUT3A x TO DOUT0A x 2 14 14 ADC A DOUT3B x TO DOUT0B x 4 DOUT3C x TO DOUT0C x LVDS DOUT3D x TO DOUT0D x BUFFER 2 14 DCO CLOCK ADC B DCO x STROBE STROBE x 2 14 ADC C DIGITAL ADC AND DAC 14 DIN6A x TO DIN0A x DATAPATHS 2 14 CONTROLS ADC D LVDS DIN6B x TO DIN0B x SPI REGISTERS BUFFER FIFO BUFFERS DCI CLOCK DCI x 2 14 DAC A 4 SPI SCLK, SPI CS, SPI SDI, SPI SDO RST 2 14 ALERT DAC B PLL 0 MxFE CLOCK GENERATOR AD9993 1 31.25MHz DIV OR 1GHz 62.5MHz Figure 1. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20142017 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com 500MHz 250MHz 500MHz 250MHz 12260-001AD9993 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 LVDS Interface Timing.............................................................. 22 Applications ....................................................................................... 1 LVDS Lane Testing Using PRBS ............................................... 23 General Description ......................................................................... 1 Power Mode Programming ....................................................... 23 Functional Block Diagram .............................................................. 1 Interrupt Request Operation .................................................... 23 Revision History ............................................................................... 3 Temperature Sensor ................................................................... 23 Specifications ..................................................................................... 4 Start-Up Register Sequences ......................................................... 25 DC Specifications ......................................................................... 4 Power-Up Routine When Using the On-Chip Clock Synthesizer .................................................................................. 25 AC Specifications .......................................................................... 5 Power-Up Routine When Using External Clock ................... 25 Digital Specifications ................................................................... 5 Applications Information .............................................................. 27 Absolute Maximum Ratings ............................................................ 7 Direct Conversion Radio Application ..................................... 27 Thermal Resistance ...................................................................... 7 Register Map ................................................................................... 28 ESD Caution .................................................................................. 7 Register Descriptions ..................................................................... 30 Pin Configuration and Function Descriptions ............................. 8 SPI Configuration Register ....................................................... 30 Typical Performance Characteristics ........................................... 11 Chip ID Register ......................................................................... 30 Receiver ADC Performance ...................................................... 11 Chip Grade Register ................................................................... 31 Transmitter DAC Performance................................................. 13 Device Index Register ................................................................ 31 Terminology .................................................................................... 15 Power Mode Control Register .................................................. 32 Theory of Operation ...................................................................... 16 Align ADC LVDS Clocks, ADC FIFO, DAC FIFO Register 32 Product Description ................................................................... 16 Strobe Lane Control Register .................................................... 33 SPI Port ........................................................................................ 16 Output Mode Register ............................................................... 33 SPI Configuration Programming ............................................. 17 LVDS Tx Control Register ........................................................ 34 Register Update Transfer Method ............................................ 17 V Control Register ................................................................. 34 REF ADC Register Update Indexing ................................................ 17 PRBS Generator Control Register ............................................ 35 ADCs ............................................................................................ 17 8-Bit Seed MSB of PRBS Generator for Lane 0 Register ....... 35 ADC Architecture ...................................................................... 17 8-Bit Seed MSB of PRBS Generator for Lane 1 Register ....... 36 ADC Section Programming ...................................................... 17 8-Bit Seed MSB of PRBS Generator for Lane 2 Register ....... 36 Analog Input Considerations .................................................... 17 8-Bit Seed MSB of PRBS Generator for Lane 3 Register ....... 36 DACs ............................................................................................ 18 Synthesizer Status Register ........................................................ 37 DAC Transfer Function ............................................................. 18 Loop Filter Control Signals Register........................................ 37 DAC Output Compliance Voltage Range and AC Performance ................................................................................ 18 Loop Filter Control Signals Register........................................ 38 DAC Voltage Reference ............................................................. 19 Loop Filter Control Signals Register........................................ 38 DAC Gain Setting ....................................................................... 19 Integer Value of Synthesizer Divider Register ........................ 39 DAC Datapath Format Selection .............................................. 19 Synthesizer Control Register .................................................... 39 DAC Test Tone Generator DDS................................................ 19 Clock Generator Control Register ........................................... 39 Clocking ....................................................................................... 20 CLKGEN Control Register ....................................................... 40 On-Chip PLL Clock Multiplier ................................................ 20 DAC LVDS Rx Control Register .............................................. 40 Selecting Clocking Options ....................................................... 21 DAC LVDS Current Bias Control Register ............................. 41 ADC Datapath and DAC Datapath FIFOs ............................. 21 DAC Cores Control Register .................................................... 42 LVDS Interfaces .......................................................................... 21 DAC Datapath Format Control Register ................................ 42 Rev. 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