Zero Drift, High Voltage, Low Power, Programmable Gain Instrumentation Amplifier Data Sheet ADA4254 FEATURES SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM Optimized for ADC synchronization VDDH Low power: 22 mW (12 V supplies) EXCITATION CURRENTS ADA4254 12 binary gain steps from 1/16 V/V to 128 V/V IOUT HV 3 scaling gains: 1 V/V, 1.25 V/V, and 1.375 V/V IOUT LV AVDD 60 V protected input multiplexer Excellent dc precision + R OUT Low input offset voltage: 14 V maximum OUT +IN1 + Low input offset voltage drift: 0.08 V/C maximum IN1 Gain calibration via ROM R VOCM IN +IN2 Low gain drift: 1 ppm/C maximum + IN2 +OUT High CMRR: 116 dB minimum, G = 1 V/V + Low input bias current: 1.5 nA maximum R OUT High input impedance AVSS Integrated input EMI filtering DIGITAL CONTROL Wide input supply range: 5 V to 28 V DVDD Dedicated output amplifier supplies DVSS 7 GPIO SPI INTERFACE 7 GPIO ports with special functions Sequential chip select mode VSSH External multiplexer control Figure 1. Excitation current sources SPI port with checksum (CRC) support Internal fault detection The input multiplexer provides 60 V protection to the high Wire break test currents impedance inputs of the amplifier, while providing the On-chip test multiplexer capability to switch between two input sources. In addition, 28-lead, 5 mm 5 mm LFCSP, 24-lead TSSOP integrated electromagnetic interference (EMI) filters block Specified temperature range: 40C to +105C harsh RF noise from the sensitive inputs of the amplifier. APPLICATIONS Various safety features on the ADA4254 detect both internal Universal process control front ends and external faults. The serial port interface (SPI) supports Data acquisition systems cyclical redundancy check (CRC) error detection to ensure Test and measurement systems robust communication. These safety features ease system safety GENERAL DESCRIPTION integrity level (SIL) certification. The ADA4254 is a zero drift, high voltage, low power Seven general-purpose input/output (GPIO) pins, which can be programmable gain instrumentation amplifier (PGIA) designed configured to provide various special functions, are included in for process control and industrial applications. The ADA4254 the ADA4254. An excitation current source output is available features 12 binary weighted gains ranging from 1/16 V/V to to bias sensors such as resistance temperature detectors (RTDs). 128 V/V and three scaling gain options of 1 V/V, 1.25 V/V, and 1.375 V/V, resulting in 36 possible gain settings. The power The ADA4254 is specified over the 40C to +105C temperature consumption of the ADA4254 is a mere 22 mW, making the range and is offered in a compact 5 mm 5 mm, 28-lead LFCSP device an excellent choice for industrial systems that demand and a 24-lead TSSOP. precision, robustness, and low power. COMPANION PRODUCTS The zero drift amplifier topology of the ADA4254 self calibrates ADCs: AD4007, AD7768, AD7175-2 dc errors and low frequency 1/f noise, achieving excellent dc ADC Drivers: ADA4945-1, LTC6363 precision over the entire specified temperature range. This high Voltage References: ADR4550, ADR3450, LT6656 level of precision maximizes dynamic range and greatly reduces calibration requirements in many applications. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. Tel: 781.329.4700 20192020 Analog Devices, Inc. All rights reserved. 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Trademarks and registered trademarks are the property of their respective owners. 60V OVERVOLTAGE PROTECTED MUX EMI FILTER 15741-001ADA4254 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 SPI Read/Write Error Detection .............................................. 35 Applications ...................................................................................... 1 SPI Command Length Error Detection .................................. 35 General Description ......................................................................... 1 Applications Information ............................................................. 36 Simplified Functional Block Diagram ........................................... 1 Input and Output Offset Voltage and Noise .......................... 36 Companion Products ....................................................................... 1 ADC Clock Synchronization .................................................... 36 Revision History ............................................................................... 3 Programmable Logic Controller (PLC) Voltage/Current Input ............................................................................................. 37 Specifications .................................................................................... 4 3-Wire RTD With Current Excitation .................................... 38 Timing Specifications .................................................................. 8 High Rail Current Sensing ........................................................ 39 Absolute Maximum Ratings ........................................................... 9 Register Summary .......................................................................... 40 Thermal Resistance ...................................................................... 9 Register Details ............................................................................... 42 ESD Caution.................................................................................. 9 GAIN MUX Register Details ................................................... 42 Pin Configurations and Function Descriptions ......................... 10 Software Reset Register (Reset) Details ................................... 43 Typical Performance Characteristics ........................................... 11 Clock Synchronization Configuration Register (SYNC CFG) Theory of Operation ...................................................................... 23 Details .......................................................................................... 44 Programmable Gain Instrumentation Amplifier .................. 23 Digital Error Register (DIGITAL ERR) Details .................... 45 Input Multiplexer ....................................................................... 24 Analog Error Register (ANALOG ERR) Details .................. 46 EMI Reduction and Internal EMI Filter ................................. 24 GPIO Data Register (GPIO DATA) Details ......................... 47 Input Amplifier ........................................................................... 25 Internal Mux Control Register (INPUT MUX) Details ...... 48 Output Amplifier........................................................................ 25 Wire Break Detect Register (WB DETECT) Details ............ 49 Power Supplies ............................................................................ 26 GPIO Direction Register (GPIO DIR) Details ..................... 50 ESD Map ...................................................................................... 26 Sequential Chip Select Register (SCS) Details ........................ 50 Output Ripple Calibration Configuration .............................. 27 Analog Error Mask Register (ANALOG ERR DIS) Details ... 51 General-Purpose Inputs/Outputs (GPIOs) ............................ 27 Digital Error Mask Register (DIGITAL ERR DIS) Details ..... 52 Excitation Currents .................................................................... 27 Special Function Configuration Register (SF CFG) Details .... 53 External Clock Synchronization .............................................. 28 Error Configuration Register ................................................... 54 Sequential Chip Select (SCS) .................................................... 28 Test Multiplexer Register (TEST MUX) Details .................. 55 Gain Error Calibration .............................................................. 30 Excitation Current Configuration Register Wire Break Detection ................................................................ 31 (EX CURRENT CFG) Details ................................................ 56 Test Multiplexer ......................................................................... 32 Gain Calibration Registers (GAIN CALx) Details ............... 57 External Mux Control ................................................................ 32 Trigger Calibration Register (TRIG CAL) Details ............... 58 Digital Interface .............................................................................. 33 Master Clock Count Register (M CLK CNT) Details ......... 58 SPI Interface ................................................................................ 33 DIE Revision Identification Register (DIE REV ID) Details Accessing the ADA4254 Register Map ................................... 33 ....................................................................................................... 58 Checksum Protection ................................................................ 33 Device Identification Registers (PART ID) Details ............. 58 CRC Calculation ......................................................................... 35 Outline Dimensions ....................................................................... 59 Memory Map Checksum Protection ....................................... 35 Ordering Guide .......................................................................... 59 Read-Only Memory (ROM) Checksum Protection .............. 35 Rev. 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