Data Sheet ADA4255 Zero Drift, High Voltage, Programmable Gain Instrumentation Amplifier with Charge Pump FEATURES The zero drift PGIA topology of the ADA4255 self calibrates dc errors and lower frequency 1/f noise, achieving excellent dc preci- Integrated bipolar charge pump sion over the entire specified temperature range. The combination of 36 precision gains ranging from 1/16 V/V to 176 V/V within the Simplified isolation requirements ADA4255 and high voltage, high impedance inputs allow a wide Wide input range on low voltage supplies range of inputs to be scaled to the range of the analog-to-digital Dedicated output amplifier supplies for ADC protection converter (ADC). By integrating all gain setting and level shifting Low power: 83 mW (DVDD = 3 V, VDDCP = 5 V) resistors, the ADA4255 achieves excellent common-mode rejection 36 precision gains from 1/16 V/V to 176 V/V ratio (CMRR) performance (111 dB minimum at G = 1 V/V) and extremely low gain drift (1 ppm/ maximum). This high level of Robust 60 V protected 2:1 input multiplexer precision maximizes dynamic range and greatly reduces calibration Excellent dc precision requirements in many applications. Low input offset voltage: 14 V maximum The 60 V input protection, integrated electromagnetic interferance Low input offset voltage drift: 0.08 V/C maximum (EMI) filtering and various safety features make the ADA4255 an Gain calibration via internal memory ideal choice for robust industrial systems. Seven general-purpose Low gain drift: 1 ppm/C maximum input and output (GPIOx) pins, which can be configured to provide various special functions, are included in the ADA4255. An excita- High CMRR: 111 dB minimum, G = 1 V/V tion current source output is available to bias sensors such as Low input bias current: 1.5 nA maximum at T = 25 A resistance temperature detectors (RTDs). Integrated input EMI filtering The ADA4255 is specified over the 40C to +105C temperature 7 GPIOx ports with special functions range and is offered in a compact 5 mm 5 mm, 28-lead LFCSP. Sequential chip select mode Excitation current source SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM SPI port with checksum (CRC) support Internal/external fault detection Compact 28-lead, 5 mm 5 mm LFCSP Specified temperature range: 40C to +105C APPLICATIONS Universal process control front ends Data acquisition systems Test and measurement systems System power monitoring GENERAL DESCRIPTION The ADA4255 is a precision programmable gain instrumentation Figure 1. Simplified Functional Block Diagram amplifier (PGIA) with integrated bipolar charge pumps. With its inte- grated charge pumps, the ADA4255 internally produces the high COMPANION PRODUCTS voltage bipolar supplies needed to achieve a wide input voltage range (38 V typical with VDDCP = 5 V) without lowering input ADCs: AD4007, AD7768, AD7175-2, AD7124-4 impedance. The charge pump topology of the ADA4255 allows ADC Drivers: ADA4945-1, LTC6363 channels to be isolated with only low voltage components, reducing Voltage References: ADR4550, ADR3450, LT6656 complexity, size, and implementation time in industrial and process Isolators: ADuM6421A Family, ADuM140D Family control systems. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliableas i. However, no responsibility is assumed by Analog DOCUMENT FEEDBACK Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and TECHNICAL SUPPORT registered trademarks are the property of their respective owners.Data Sheet ADA4255 TABLE OF CONTENTS Features................................................................ 1 3-Wire RTD With Current Excitation.................42 Applications........................................................... 1 High Rail Current Sensing................................43 General Description...............................................1 Register Summary...............................................44 Simplified Functional Block Diagram.....................1 Register Details................................................... 46 Companion Products.............................................1 Gain Multiplexer Register (GAIN MUX) Specifications........................................................ 4 Details............................................................ 46 Timing Specifications......................................... 8 Software Reset Register (Reset) Details..........47 Absolute Maximum Ratings...................................9 Clock Synchronization Configuration Thermal Resistance........................................... 9 Register (SYNC CFG) Details.......................48 ESD Caution.......................................................9 Digital Error Register (DIGITAL ERR) Pin Configurations and Function Descriptions.....10 Details............................................................ 49 Typical Performance Characteristics................... 11 Analog Error Register (ANALOG ERR) Theory of Operation.............................................25 Details............................................................ 50 Programmable Gain Instrumentation GPIO Data Register (GPIO DATA) Details......51 Amplifier......................................................... 25 Internal Mux Control Register Input Multiplexer...............................................26 (INPUT MUX) Details.................................... 52 EMI Reduction and the Internal EMI Filter....... 26 Wire Break Detect Register (WB DETECT) Input Amplifier.................................................. 27 Details............................................................ 53 Output Amplifier................................................27 GPIO Direction Register (GPIO DIR) Details.. 54 Power Supplies................................................ 28 Sequential Chip Select Register (SCS) ESD Map..........................................................28 Details............................................................ 54 Output Ripple Calibration Configuration...........29 Analog Error Mask Register General-Purpose Inputs and Outputs (ANALOG ERR DIS) Details........................ 55 (GPIOs).......................................................... 29 Digital Error Mask Register Excitation Currents...........................................30 (DIGITAL ERR DIS) Details..........................56 External Clock Synchronization .......................30 Special Function Configuration Register Sequential Chip Select (SCS).......................... 30 (SF CFG) Details...........................................57 Gain Error Calibration.......................................32 Error Configuration Register (ERR CFG) Wire Break Detection....................................... 34 Details............................................................ 58 Test Multiplexer................................................ 35 Test Multiplexer Register (TEST MUX) External Mux Control........................................35 Details............................................................ 59 Digital Interface....................................................36 Excitation Current Configuration Register SPI....................................................................36 (EX CURRENT CFG) Details.......................61 Accessing the ADA4255 Register Map............ 36 Gain Calibration Registers (GAIN CALx) Checksum Protection....................................... 36 Details............................................................ 62 CRC Calculation...............................................38 Trigger Calibration Register (TRIG CAL) Memory Map Checksum Protection................. 38 Details............................................................ 63 Read-Only Memory (ROM) Checksum Master Clock Count Register Protection....................................................... 38 (M CLK CNT) Details....................................63 SPI Read and Write Error Detection................ 38 DIE Revision Identification Register SPI Command Length Error Detection.............38 (DIE REV ID) Details....................................63 Applications Information...................................... 39 Device Identification Registers (PART ID) Input and Output Offset Voltage and Noise......39 Details............................................................ 63 ADC Clock Synchronization............................. 39 Outline Dimensions............................................. 64 Programmable Logic Controller (PLC) Ordering Guide.................................................64 Voltage and Current Input.............................. 41 Evaluation Boards............................................ 64 analog.com Rev. 0 2 of 64