Low Distortion, DOCSIS 3.0, Upstream CATV Line Driver ADA4320-1 FEATURES FUNCTIONAL BLOCK DIAGRAM Supports CableLabs DOCSIS 3.0/2.0 and EuroDOCSIS VIN VOUT+ 3.0/2.0 specifications for customer premises equipment DIFF OR ATTENUATION POWER SINGLE VERNIER (CPE) upstream transmission CORE AMP INPUT AMP 5 V single-supply operation VIN+ VOUT Z DIFF = OUT 8 Excellent adjacent channel rejection performance 300 Z (SINGLE) = 320 IN DECODE Z (DIFF) = 640 66 dBc ACPR for a single QPSK channel IN 8 POWER-DOWN 63 dBc ACPR for 4 QAM64 channels RAMP DATA LATCH LOGIC Gain programmable in 1 dB steps over a 59 dB range 8 ADA4320-1 SHIFT Gain range: 27 dB to +32 dB REGISTER Current-scaled output stage GND DATEN SDATA CLK TXEN SLEEP Low between-burst output noise level Figure 1. 70 dB mV in 160 kHz bandwidth Maintains constant output impedance in enable, disable, and sleep conditions Selectable low power modes 12 mA in Tx disable 12 A in sleep mode (full power-down) 3-wire, SPI-compatible interface 4 mm 5 mm 24-lead LFCSP, RoHS compliant APPLICATIONS DOCSIS 3.0 and EuroDOCSIS cable modems/E-MTAs DOCSIS 3.0 set-top boxes CATV telephony modems Coaxial or twisted pair line drivers GENERAL DESCRIPTION The ADA4320-1 is a high power, ultralow distortion amplifier The ADA4320-1 features an output driver stage that scales designed for CATV reverse channel line driving. Its features and quiescent current consumption according to gain setting. In specifications make the ADA4320-1 ideally suited for DOCSIS 3.0- multichannel mode at maximum gain (32 dB), the device draws and EuroDOCSIS 3.0-based applications. Both gain and output 260 mA from a single 5 V supply, enabling the high power, stage current are controlled via a 3-wire (SPI-compatible) interface. ultralow distortion performance required by multiple DOCSIS 3.0 A single 8-bit serial word selects one of four available supply upstream channels. For lifeline E-MTA applications, the ADA4320-1 current presets and one of sixty gain codes. output stage current can be throttled via SPI commands, reducing the power requirement for single-channel transmission by up to The ADA4320-1 has been tailored to address both the high output 30%. In transmit-disable mode, the ADA4320-1 draws only 12 mA. drive and stringent fidelity requirements of DOCSIS 3.0. The The device also features a full power-down sleep mode that part is able to maintain excellent adjacent channel rejection further reduces current draw to12 A typical. performance over the full 5 MHz to 85 MHz range, even with multiple bonded channels at maximum specified output levels. The ADA4320-1 is packaged in a RoHS-compliant, 24-lead exposed pad LFCSP and is rated for operation over the 40C The ADA4320-1 accepts a differential or single-ended input to +85C temperature range. signal. The output is specified for driving a single-ended 75 load through a 4:1 impedance transformer. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. 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Trademarks and registered trademarks are the property of their respective owners. 08707-001ADA4320-1 TABLE OF CONTENTS Features .............................................................................................. 1 General Applications ................................................................. 11 Applications ....................................................................................... 1 Circuit Description .................................................................... 11 Functional Block Diagram .............................................................. 1 Programming .............................................................................. 11 General Description ......................................................................... 1 Current Level and Gain Adjustment ....................................... 11 Revision History ............................................................................... 2 Power Saving Features ............................................................... 12 Specif icat ions ..................................................................................... 3 Input Bias, Impedance, and Termination ................................ 12 Logic Inputs (TTL-/CMOS-Compatible Logic) ....................... 4 Output Bias, Impedance, and Termination ............................ 12 Timing Requirements .................................................................. 5 Power Supply ............................................................................... 12 Absolute Maximum Ratings ............................................................ 6 Signal Integrity Layout Considerations ................................... 12 Thermal Resistance ...................................................................... 6 Initial Power-Up ......................................................................... 12 Maximum Power Dissipation ..................................................... 6 RAMP Pin Feature ..................................................................... 13 ESD Caution .................................................................................. 6 Output Transformer ................................................................... 13 Pin Configuration and Function Descriptions ............................. 7 Outline Dimensions ....................................................................... 14 Typical Performance Characteristics ............................................. 8 Ordering Guide .......................................................................... 14 Applications Information .............................................................. 11 REVISION HISTORY 10/10Rev. 0 to Rev. A Changes to Product Title ................................................................. 1 Changes to Pin 14, Description, Table 6 ........................................ 7 Changes to Current Level and Gain Adjustment Section ......... 11 Changes to Output Bias, Impedance, and Termination Section ....................................................................... 12 Changes to Figure 24 ...................................................................... 13 Changes to Ordering Guide .......................................................... 14 4/10Revision 0: Initial Version Rev. A Page 2 of 16