Programmable Transimpedance, Current to Bits Receiver Module Data Sheet ADA4355 FEATURES GENERAL DESCRIPTION High performance, current input, data acquisition Module The ADA4355 is a complete, high performance, current input that includes a TIA, analog filter, ADC driver, and ADC Module. For space savings, the ADA4355 includes all the 3 selectable TZ settings: 2 k, 20 k, and 200 k required active and passive components to realize a complete Internal 1.8 V LDO for the ADC current to bits data acquisition solution, supporting a small All passive components including supply decoupling form factor, optical modules as well as multichannel systems. Small form factor: 12.00 mm 6.00 mm CSP BGA The high speed transimpedance amplifier (TIA) of the device Operation from a single 3.3 V supply supports 10 ns pulse widths, allowing high spatial resolution for Full-scale input current to 800 A (TZ = 2 k) Time of Flight (ToF) measurements. Additionally, the ADA4355 Fast input overload recovery includes three TIA gain (T ) settings to maximize dynamic range. High analog input current to 40 mA Z Analog filter for noise reduction and antialias filtering An internal, selectable, analog low-pass filter (LPF) can limit Selectable 1.0 MHz and 100 MHz LPF bandwidth the device bandwidth with a corner frequency of 100 MHz to Low input referred current noise: 16 pA rms minimize broadband noise while also serving as an antialiasing TZ = 200 k, 65 ,536 averages, 1 MHz analog filter filter for the 125 MSPS ADC. For lower bandwidth signals, or Supports input pulse widths down to 10 ns wider signal pulses (for example, 20 s or wider), the filter can 14-bit ADC with sample rate up to 125 MSPS be set to a corner frequency of 1.0 MHz to provide additional Serial LVDS data output noise reduction. SPI control interface The 14-bit ADC converts the amplified voltage signal at a rate of Quiescent power: 546 mW, LDO enabled up to 125 MSPS and outputs the digitized signals through two Temperature range: 40C to +85C serial, low voltage differential signaling (LVDS) data lanes, APPLICATIONS operating at rates of up to 1 Gbps per lane. The data clock Current to voltage conversion output (DCO) operates at frequencies of up to 500 MHz and Chemical analyzers supports double data rate (DDR) operation. Mass spectroscopy The ADA4355 exhibits fast overdrive recovery from a large Time of Flight input current signal and is available in a 12.00 mm 6.00 mm Fiber optic sensing CSP BGA package with a 40C to +85C operating temperature OTDR range. Optical amplifiers Reconfigurable optical add and drop multiplexers (ROADM) FUNCTIONAL BLOCK DIAGRAM VCC VLDEN VLD VEA/VED 2 LDO BANDWIDTH LVDS LANES INPUT TIA ADC LPF SPI SIGNALS SPI 2 GSEL0, ADA4355 GSEL1 FSEL GND CLKN CLKP Figure 1. Rev. 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Technical Support www.analog.com 23165-001ADA4355 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Power and Power Control......................................................... 27 Applications ...................................................................................... 1 Clocks ........................................................................................... 27 General Description ......................................................................... 1 Clock Stability Considerations ................................................. 29 Functional Block Diagram .............................................................. 1 Controls ....................................................................................... 29 Revision History ............................................................................... 2 Digital Output and Timing ....................................................... 29 Specifications .................................................................................... 3 OTDR Performance ................................................................... 33 Performance Specifications......................................................... 3 PCB Design Tips ........................................................................ 36 Power Specifications .................................................................... 4 SPI ..................................................................................................... 37 CLK, SPI, and Control Specifications ....................................... 5 Configuration Using the SPI .................................................... 37 ADC SPI Timing Specifications ................................................. 6 ADC SPI Start-Up Sequence .................................................... 37 ADC LVDS Output Specifications ............................................ 7 Hardware Interface .................................................................... 37 Absolute Maximum Ratings ......................................................... 13 SPI Accessible Features ............................................................. 37 Thermal Resistance .................................................................... 13 Memory Map .................................................................................. 38 ESD Caution................................................................................ 13 Overview ...................................................................................... 38 Pin Configuration and Function Descriptions .......................... 14 Memory Map Register Table .................................................... 39 Typical Performance Characteristics ........................................... 15 Memory Map Register Descriptions ....................................... 42 Equivalent Circuits ......................................................................... 25 Outline Dimensions ....................................................................... 45 Theory of Operation ...................................................................... 26 Ordering Guide .......................................................................... 45 Applications Information .............................................................. 27 REVISION HISTORY 10/2020Revision A: Initial Version Rev. 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