Femtoampere Input Bias Current Electrometer Amplifier Data Sheet ADA4530-1 FEATURES PIN CONNECTION DIAGRAM ADA4530-1 Low input bias current 20 fA maximum at T = 25C (guaranteed at production test) A +IN 1 8 IN 20 fA maximum at 40C < T < +85C A GRD 2 7 GRD 250 fA maximum at 40C < T < +125C (guaranteed at A 6 OUT IC 3 production test) V 4 5 V+ Low offset voltage: 50 V maximum over specified CMRR range NOTES Offset voltage drift: 0.13 V/C typical, 0.5 V/C maximum 1. IC = INTERNAL CONNECTION. THIS PIN MUST BE CONNECTED TO V Integrated guard buffer with 100 V maximum offset OR LEFT UNCONNECTED. Low voltage noise density: 14 nV/Hz at 10 kHz Figure 1. Wide bandwidth: 2 MHz unity-gain crossover Supply voltage: 4.5 V to 16 V (2.25 V to 8 V) Operating temperature: 40C to +125C Long-term offset voltage drift (10,000 hours): 0.5 V typical Temperature hysteresis: 1.5 V typical APPLICATIONS Laboratory and analytical instrumentation: spectrophoto- meters, chromatographs, mass spectrometers, and potentiostatic and amperostatic coulometry Instrumentation: picoammeters and coulombmeters Transimpedance amplifier (TIA) for photodiodes, ion chambers, and working electrode measurements High impedance buffering for chemical sensors and capacitive sensors GENERAL DESCRIPTION 15 The ADA4530-1 is a femtoampere (10 A) level input bias To maximize the dynamic range of the system, the ADA4530-1 current operational amplifier suitable for use as an electrometer has a rail-to-rail output stage that can typically drive to within that also includes an integrated guard buffer. It has an operating 30 mV of the supply rails under a 10 k load. voltage range of 4.5 V to 16 V, enabling it to operate in conven- The ADA4530-1 operates over the 40C to +125C industrial tional 5 V and 10 V single supply systems as well as 2.5 V and temperature range and is available in an 8-lead SOIC package. 5 V dual supply systems. 1000 40C TO +125C LIMIT V = 10V SY It provides ultralow input bias currents that are production V = V /2 CM SY RH < 10% 100 tested at 25C and at 125C to ensure the device meets its perfor- 40C TO +85C LIMIT mance goals in user systems. The integrated guard buffer 10 isolates the input pins from leakage in the printed circuit board (PCB), minimizes board component count, and enables easy 1 system design. The ADA4530-1 is available in an industry- standard surface-mount 8-lead SOIC package with a unique 0.1 I + pinout optimized to prevent signals from coupling between the B I B sensitive input pins, the power supplies, and the output pin 0.01 while enabling easy routing of the guard ring traces. The ADA4530-1 also offers low offset voltage, low offset drift, 0.001 0 10 20 30 40 50 60 70 80 90 100 110 120 130 and low voltage and current noise needed for the types of TEMPERATURE (C) applications that require such low leakages. Figure 2. Input Bias Current (IB) vs. Temperature, VSY = 10 V Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. 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Technical Support www.analog.com I (fA) B 13405-001 13405-202ADA4530-1 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Input Resistance.......................................................................... 34 Applications ....................................................................................... 1 Input Offset Voltage ................................................................... 34 Pin Connection Diagram ................................................................ 1 Insulation Resistance ................................................................. 34 General Description ......................................................................... 1 Guarding ...................................................................................... 35 Revision History ............................................................................... 3 Dielectric Relaxation .................................................................. 35 Specifications ..................................................................................... 4 Humidity Effects ......................................................................... 37 5 V Nominal Electrical Characteristics ..................................... 4 Contamination ............................................................................ 38 10 V Nominal Electrical Characteristics ................................... 6 Cleaning and Handling ............................................................. 39 15 V Nominal Electrical Characteristics ................................... 8 Solder Paste Selection ................................................................ 39 Absolute Maximum Ratings .......................................................... 10 Current Noise Considerations ...................................................... 40 Thermal Resistance .................................................................... 10 Layout Guidelines ........................................................................... 43 ESD Caution ................................................................................ 10 Physical Implementation of Guarding Techniques................ 43 Pin Configuration and Function Descriptions ........................... 11 Guard Ring .................................................................................. 43 Typical Performance Characteristics ........................................... 12 Guard Plane ................................................................................. 43 Main Amplifier, DC Performance ............................................ 12 Via Fence ..................................................................................... 44 Main Amplifier, AC Performance ............................................ 21 Cables and Connectors .............................................................. 44 Guard Amplifier ......................................................................... 27 Electrostatic Interferance .......................................................... 44 Theory of Operation ...................................................................... 29 Photodiode Interface ...................................................................... 45 ESD Structure .............................................................................. 29 DC Error Analysis ...................................................................... 45 Input Stage ................................................................................... 29 AC Error Analysis ...................................................................... 45 Gain Stage .................................................................................... 30 Noise Analysis ............................................................................. 46 Output Stage ................................................................................ 30 Design Recommendations ........................................................ 47 Guard Buffer ............................................................................... 30 Design Example .......................................................................... 47 Applications Information .............................................................. 31 Power Supply Recommendations ................................................. 50 Input Protection .......................................................................... 31 Power Supply Considerations ................................................... 50 Single-Supply and Rail-to-Rail Output ................................... 31 Long-Term Drift ......................................................................... 51 Capacitive Load Stability ........................................................... 31 Temperature Hysteresis ............................................................. 51 EMI Rejection Ratio ................................................................... 32 Outline Dimensions ....................................................................... 52 High Impedance Measurements ................................................... 33 Ordering Guide .......................................................................... 52 Input Bias Current ...................................................................... 33 Rev. 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