36 V, 18 MHz, Low Noise, Fast Settling Single Supply, RRO, JFET Op Amp Data Sheet ADA4625-1/ADA4625-2 FEATURES PIN CONFIGURATION Wide gain bandwidth product: 18 MHz typical ADA4625-1 NC 1 8 NC High slew rate: 48 V/s typical IN 2 7 V+ Low voltage noise density: 3.3 nV/Hz typical at 1 kHz +IN 3 6 OUT Low peak-to-peak noise: 0.15 V p-p, 0.1 Hz to 10 Hz TOP VIEW (Not to Scale) Low input bias current: 15 pA typical at T = 25C A V 4 5 NC Low offset voltage: 80 V maximum at T = 25C A NOTES 1. NC = NO CONNECTION. DO NOT CONNECT TO THIS PIN. Offset voltage drift: 1.2 V/C maximum at T = 40C to 85C A 2. EXPOSED PAD. CONNECT THE EXPOSED PAD TO GND, V+ OR V PLANE, OR LEAVE IT FLOATING. Fast settling: 0.01% in 700 ns typical Wide range of operating voltages Figure 1. Dual-supply operation: 2.5 V to 18 V The ADA4625-1/ADA4625-2 are unity-gain stable, and there is Single-supply operation: 5 V to 36 V no phase reversal when input range exceeds either supply rail by Input voltage range includes V 200 mV. The output is capable of driving loads up to 1000 pF Rail-to-rail output and/or 600 loads. High capacitive load drive capability The ADA4625-1/ADA4625-2 are specified for operation over Output short-circuit current: 46 mA the extended industrial temperature range of 40C to +125C No phase reversal and operates from +5 V to +36 V (2.5 V to 18 V) with specifi- Unity-gain stable cations at +5 V and 18 V. The devices are available in an 8-lead APPLICATIONS SOIC package with an exposed pad (EPAD). PLL filter amplifiers 100 V = 5V SY Transimpedance amplifiers V = 18V SY Photodiode sensor interfaces Low noise charge amplifiers GENERAL DESCRIPTION The ADA4625-1/ADA4625-2 build on Analog Devices, Inc., 10 high voltage, single-supply, rail-to-rail output (RRO), precision junction field effect transistor (JFET) input op amps, taking that product type to a level of speed and low noise that has not been made available to the market previously. The ADA4625-1/ADA4625-2 provide optimal performance in 1 high voltage, high gain, and low noise applications. The input 1 10 100 1k 10k 100k common-mode voltage range includes the negative supply, and FREQUENCY (Hz) the output swings rail to rail. This enables the user to maximize Figure 2. Voltage Noise Density vs. Frequency dynamic input range in low voltage, single supply applications Table 1. Related Precision JFET Operational Amplifiers without the need for a separate negative voltage power supply Single Dual Quad for ground sense. Not applicable AD823A Not applicable The combination of wide bandwidth, low noise, and low input AD8510 AD8512 AD8513 bias current makes the ADA4625-1/ADA4625-2 especially AD8610 AD8620 Not applicable suitable for phase-locked loop (PLL), active filter amplifiers and ADA4610-1 ADA4610-2 ADA4610-4 for high tuning voltage (VTUNE), voltage controlled oscillators ADA4622-1 ADA4622-2 ADA4622-4 (VCOs) and preamplifiers where low level signals require an ADA4627-1/ADA4637-1 Not applicable Not applicable amplifier that provides both high amplification and wide bandwidth. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20172019 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. VOLTAGE NOISE DENSITY (nV/Hz) 15893-001 15893-157ADA4625-1/ADA4625-2 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Output Stage ................................................................................ 23 Applications ....................................................................................... 1 No Phase Inversion .................................................................... 24 General Description ......................................................................... 1 Supply Current ............................................................................ 24 Pin Configuration ............................................................................. 1 Applications Information .............................................................. 25 Revision History ............................................................................... 2 Active Loop Filter for Phase-Locked Loops (PLLs) .............. 25 Specifications ..................................................................................... 3 ADA4625-1 Advantages and Design Example ....................... 26 Electrical Characteristics18 V Operation ........................... 3 Transimpedance Amplifier ....................................................... 27 Electrical Characteristics5 V Operation................................ 5 DAC Output Driver ................................................................... 31 Absolute Maximum Ratings ............................................................ 7 Recommended Power Solution ................................................ 32 Thermal Resistance ...................................................................... 7 Input Overvoltage Protection ................................................... 32 ESD Caution .................................................................................. 7 Driving Capacitive Loads .......................................................... 32 Pin Configurations and Function Descriptions ........................... 8 Thermal Management ............................................................... 32 Typical Performance Characteristics ............................................. 9 Typical Applications ................................................................... 33 Theory of Operation ...................................................................... 23 Outline Dimensions ....................................................................... 35 Input and Gain Stages ................................................................ 23 Ordering Guide .......................................................................... 35 REVISION HISTORY 6/2019Rev. 0 to Rev. A Added Figure 77 and Figure 80 .................................................... 21 Added ADA4625-2 ........................................................ Throughout Added Figure 84 ............................................................................. 22 Added DAC Output Driver Section, Figure 105, Figure 106, and Changes to Table 2 ............................................................................ 3 Changes to Table 3 ............................................................................ 5 Figure 107 ........................................................................................ 31 Added Figure 4 and Table 7 Renumbered Sequentially ............. 8 Added Typical Applications Section, Figure 109, and Changes to Table 6 ............................................................................ 8 Figure 110 ......................................................................................... 33 Added Figure 16 .............................................................................. 10 Added Figure 111 and Figure 112 ................................................ 34 Added Figure 25 and Figure 28..................................................... 12 Updated Outline Dimensions ....................................................... 35 Added Figure 17, Figure 38, and Figure 40 ................................. 14 Changes to Ordering Guide .......................................................... 35 Added Figure 61 and Figure 64..................................................... 18 10/2017Revision 0: Initial Version Added Figure 65 to Figure 70 ........................................................ 19 Added Figure 73 and Figure 76..................................................... 20 Rev. A Page 2 of 35