3.1 nV/Hz, 1 mA, 180 MHz, Rail-to-Rail Input/Output Amplifiers Data Sheet ADA4807-1/ADA4807-2/ADA4807-4 FEATURES PIN CONNECTION DIAGRAMS Low input noise V 1 6 +V OUT S 3.1 nV/Hz at f = 100 kHz with 29 Hz 1/f corner 0.7 pA/Hz at f = 100 kHz with 2 kHz 1/f corner V 2 5 S DISABLE High speed performance with dc precision +IN 3 4 IN 180 MHz, 3 dB bandwidth (G = +1, V = 20 mV p-p) OUT 225 V/s slew rate for 5 V step (rise) Figure 1. 6-Lead SC70 and 6-Lead SOT-23 Pin Configuration (ADA4807-1) 47 ns settling time to 0.1% for 4 V step V 1 8 +V OUT1 S 125 V and 3.7 V/C maximum input offset voltage and drift IN1 2 7 V OUT2 100 nA and 250 pA/C maximum input offset current and drift +IN1 3 6 IN2 Low distortion (HD2/HD3), V = 5 V, V = 2 V p-p S OUT V 4 5 +IN2 S 141 dBc/144 dBc at 1 kHz Figure 2. 8-Lead MSOP Pin Configuration (ADA4807-2) 112 dBc/115 dBc at 100 kHz 95 dBc/79 dBc at 1 MHz 10 +V V 1 S OUT1 9V IN1 2 OUT2 Low power operation 3 8IN2 +IN1 1.0 mA quiescent supply current per amplifier at 5 V V 4 7+IN2 S DISABLE1 5 6 DISABLE2 Dynamic power scaling Fully specified at +3 V, +5 V, and 5 V supplies Figure 3. 10-Lead LFCSP Pin Configuration (ADA4807-2) Rail-to-rail inputs and outputs 1 14 V V OUT1 OUT4 APPLICATIONS IN1 2 13 IN4 High resolution analog-to-digital converter (ADC) drivers 3 +IN1 12 +IN4 Portable and battery-powered instruments and systems 4 11 +V ADA4807-4 V S S High component density data acquisition systems 5 10 +IN3 +IN2 Audio signal conditioning 6 IN2 9 IN3 Active filters 7 8 V V OUT2 OUT3 Figure 4. 14-Lead TSSOP Pin Configuration (ADA4807-4) GENERAL DESCRIPTION The ADA4807-1 (single), ADA4807-2 (dual), and ADA4807-4 These amplifiers are fully specified at +3 V, +5 V, and 5 V supplies (quad) are low noise, rail-to-rail input and output, voltage and can operate over the industrial 40C to +125C feedback amplifiers. These amplifiers combine low power, low temperature range. noise, high speed, and dc precision to provide an attractive The ADA4807-1 is available in 6-lead SOT-23 and space-saving solution for a wide range of applications from high resolution 6-lead SC70 packages. The ADA4807-2 is available in an 8-lead data acquisition instrumentation to high performance battery- MSOP and a compact, 3 mm 3 mm, 10-lead LFCSP. The powered and high component density systems where power ADA4807-4 is available in a 14-lead TSSOP package. consumption is of key importance. Table 1. Other Rail-to-Rail Amplifiers With only 1.0 mA of supply current per amplifier, the ADA4807-1/ Slew Voltage Max. ADA4807-2/ADA4807-4 feature the lowest input voltage noise Bandwidth Rate Noise VOS among high speed, rail-to-rail input/output amplifiers in the Device (MHz) (V/s) (nV/Hz) (mV) industry and offer a wide bandwidth, high slew rate, fast settling AD8031/AD8032 80 35 15 1.5 time, and excellent distortion performance. Additionally, these AD8027/AD8028 190 90 4.3 0.8 amplifiers offer very low input offset voltage and drift performance, AD8029/AD8030/ 125 62 16.5 5 making them ideal for driving multiplexed and high throughput AD8040 precision 16-/18-bit successive approximation registers (SARs) and 24-bit - ADCs. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20142015 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 12611-058 12611-001 12611-104 12611-059ADA4807-1/ADA4807-2/ADA4807-4 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Slew, Transient, Settling Time, and Crosstalk ............................. 18 Applications ....................................................................................... 1 Distortion and Noise .................................................................. 20 Pin Connection Diagrams ............................................................... 1 Output Characteristics............................................................... 22 General Description ......................................................................... 1 Overdrive Recovery and Turn On/Turn Off Times .............. 23 Revision History ............................................................................... 2 Theory of Operation ...................................................................... 24 Specif icat ions ..................................................................................... 3 Disable Circuitry ........................................................................ 25 5 V Supply ................................................................................... 3 Input Protection ......................................................................... 25 5 V Supply ...................................................................................... 5 Noise Considerations ................................................................. 25 3 V Supply ...................................................................................... 7 Applications Information .............................................................. 26 Absolute Maximum Ratings ............................................................ 9 Capacitive Load Drive ............................................................... 26 Maximum Power Dissipation ..................................................... 9 Low Noise FET Operational Amplifier ................................... 26 Thermal Resistance ...................................................................... 9 Power Mode ADC Driver ......................................................... 27 ESD Caution .................................................................................. 9 ADC Driving ............................................................................... 28 Pin Configurations and Function Descriptions ......................... 10 ADC Driving with Dynamic Power Scaling ........................... 29 Typical Performance Characteristics ........................................... 13 Layout, Grounding, and Bypassing .......................................... 30 Frequency Response ................................................................... 13 Outline Dimensions ....................................................................... 31 Frequency and Supply Current ................................................. 15 Ordering Guide .......................................................................... 33 DC and Input Common-Mode Performance ......................... 16 REVISION HISTORY 9/15Rev. A to Rev. B Added Figure 58 ............................................................................. 33 Added ADA4807-4 ............................................................. Universal Changes to Ordering Guide .......................................................... 33 Changes to Features Section, General Description Section, and Table 1 .......................................................................................................... 1 4/15Rev. 0 to Rev. A Added Figure 4, Renumbered Sequentially .................................. 1 Added ADA4807-2 ............................................................. Universal Changes to Table 2 ............................................................................ 3 Changes to Features Section, General Description Changes to Table 3 ............................................................................ 5 Section, and Pin Connection Diagrams Heading ......................... 1 Changes to Table 4 ............................................................................ 7 Added Figure 2 and Figure 3 Renumbered Sequentially ............ 1 Deleted Figure 6, Renumbered Sequentially ............................... 10 Changes to Table 1 ............................................................................. 3 Changes to Figure 6 ........................................................................ 10 Changes to Table 2 ............................................................................. 5 Added Figure 9 and Table 9, Renumbered Sequentially ........... 12 Changes to Table 3 ............................................................................. 7 Changes to Figure 20 ...................................................................... 14 Changes to Table 6 and Figure 4 ...................................................... 9 Added Figure 21 .............................................................................. 14 Added Figure 7, Figure 8, and Table 8 Renumbered Sequentially .... 11 Added Figure 31 and Figure 32..................................................... 16 Reorganized Layout, Typical Performance Characteristics Added Figure 35 .............................................................................. 17 S ection .............................................................................................. 12 Changes to Figure 39 ...................................................................... 18 Added Figure 36 ............................................................................. 16 Added Figure 42 .............................................................................. 19 Changes to Figure 37 Caption, Figure 38 Caption, Figure 39 Deleted Figure 50, Figure 51, Figure 53, and Figure 54 ............. 19 Caption, and Figure 40 Caption ................................................... 17 Added Figure 46 .............................................................................. 20 Changes to Figure 44 and Figure 47............................................. 18 Added Figure 49 and Figure 51..................................................... 21 Change to Theory of Operation Section ..................................... 20 Added Figure 59 and Figure 61..................................................... 23 DISABLE Changes to Circuitry Section, Table 9, and Noise DISABLE Changes to Circuitry Section ...................................... 25 Considerations Section .................................................................. 21 Added Low Noise FET Operational Amplifier Section ............. 26 Added Figure 65 and Figure 66 .................................................... 23 Added Figure 70, Figure 71, Figure 72, and Power Mode ADC Changes to Ordering Guide .......................................................... 25 Driver Section ................................................................................. 27 Added ADC Driving Section and Figure 73 through Figure 77 ..... 28 12/14Revision 0: Initial Version Added ADC Driving with Dynamic Power Scaling Section, Figure 78, Figure 79, and Figure 80 .............................................. 29 Rev. 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