Ultralow Noise Drivers for Low Voltage ADCs Data Sheet ADA4930-1/ADA4930-2 FEATURES FUNCTIONAL BLOCK DIAGRAMS Low input voltage noise: 1.2 nV/Hz Low common-mode output: 0.9 V on single supply Extremely low harmonic distortion ADA4930-1 FB 1 12 PD 104 dBc HD2 at 10 MHz +IN 2 11 OUT 79 dBc HD2 at 70 MHz IN 3 10 +OUT 73 dBc HD2 at 100 MHz 4 9 V +FB OCM 101 dBc HD3 at 10 MHz 82 dBc HD3 at 70 MHz 75 dBc HD3 at 100 MHz Figure 1. High speed 3 dB bandwidth of 1.35 GHz, G = 1 Slew rate: 3400 V/s, 25% to 75% 0.1 dB gain flatness to 380 MHz IN1 1 18 +OUT1 Fast overdrive recovery of 1.5 ns 2 V +FB1 17 OCM1 0.5 mV typical offset voltage V +V 3 16 S1 S2 ADA4930-2 V Externally adjustable gain +V 4 15 S2 S1 PD2 FB2 5 14 Differential-to-differential or single-ended-to-differential 6 OUT2 +IN2 13 operation Adjustable output common-mode voltage Single-supply operation: 3.3 V or 5 V APPLICATIONS Figure 2. 100 ADC drivers Single-ended-to-differential converters IF and baseband gain blocks Differential buffers 10 Line drivers GENERAL DESCRIPTION The ADA4930-1/ADA4930-2 are very low noise, low distortion, 1 high speed differential amplifiers. They are an ideal choice for driving 1.8 V high performance ADCs with resolutions up to 14 bits from dc to 70 MHz. The adjustable output common 0 mode allows the ADA4930-1/ADA4930-2 to match the input of 10 100 1k 10k 100k 1M 10M 100M the ADC. The internal common-mode feedback loop provides FREQUENCY (Hz) Figure 3. Voltage Noise Spectral Density exceptional output balance, suppression of even-order harmonic The low dc offset and excellent dynamic performance of the distortion products, and dc level translation. ADA4930-1/ADA4930-2 make them well suited for a wide With the ADA4930-1/ADA4930-2, differential gain configurations variety of data acquisition and signal processing applications. are easily realized with a simple external feedback network of The ADA4930-1 is available in a Pb-free, 3 mm 3 mm 16-lead four resistors determining the closed-loop gain of the amplifier. LFCSP, and the ADA4930-2 is available in a Pb-free, 4 mm 4 mm The ADA4930-1/ADA4930-2 are fabricated using Analog Devices, 24-lead LFCSP. The pinout has been optimized to facilitate printed Inc., proprietary silicon-germanium (SiGe), complementary circuit board (PCB) layout and minimize distortion. The bipolar process, enabling them to achieve very low levels of ADA4930-1 is specified to operate over the 40C to +105C distortion with an input voltage noise of only 1.2 nV/Hz. temperature range, and the ADA4930-2 is specified to operate over the 40C to +105C temperature range for 3.3 V or 5 V supply voltages. Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20102017 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. V (nV/ hz) N IN2 7 24 +IN1 V +V 5 16 S S 8 23 +FB2 FB1 6 15 V V +V S +V 9 22 S S2 S1 V 14 V +V 10 21 +V 7 S2 S1 S S V 11 20 PD1 OCM2 8 13 V +V S S 19 OUT1 +OUT2 12 09209-001 09209-002 09209-003ADA4930-1/ADA4930-2 Data Sheet TABLE OF CONTENTS Features........................................................................................... 1 Test Circuits ................................................................................. 15 Applications ................................................................................... 1 Operational Description ............................................................. 16 General Description ...................................................................... 1 Definition of Terms ................................................................. 16 Functional Block Diagrams .......................................................... 1 Theory of Operation.................................................................... 17 Revision History ............................................................................ 2 Analyzing an Application Circuit ........................................... 17 Specifications ................................................................................. 3 Setting the Closed-Loop Gain ................................................ 17 3.3 V Operation ......................................................................... 3 Estimating the Output Noise Voltage..................................... 17 3.3 V V to V Performance ............................................. 4 Impact of Mismatches in the Feedback Networks ................ 18 OCM O, cm 3.3 V General Performance....................................................... 4 Input Common-Mode Voltage Range.................................... 18 5 V Operation ............................................................................ 5 Minimum R Value.................................................................. 19 G 5 V VOCM to VO, cm Performance ................................................ 6 Setting the Output Common-Mode Voltage ......................... 19 5 V General Performance.......................................................... 6 Calculating the Input Impedance for an Application Circuit ................................................................................................... 19 Absolute Maximum Ratings ......................................................... 7 Layout, Grounding, and Bypassing ............................................ 23 Thermal Resistance ................................................................... 7 High Performance ADC Driving ............................................... 24 Maximum Power Dissipation ................................................... 7 Outline Dimensions .................................................................... 25 ESD Caution............................................................................... 7 Ordering Guide........................................................................ 25 Pin Configurations and Function Descriptions .......................... 8 Typical Performance Characteristics............................................ 9 REVISION HISTORY 11/2017Rev. C to Rev. D 1/2015Rev. A to Rev. B Updated Outline Dimensions ......................................................25 Updated Outline Dimensions ......................................................25 Changes to Ordering Guide .........................................................25 Changes to Ordering Guide .........................................................25 5/2017Rev. B to Rev. C 10/2010Rev. 0 to Rev. A Changes to Figure 5 and Figure 6 .....................................................8 Changes to General Description Section ......................................1 Changes to Input Common-Mode Adjustment with DC Biased Source Section ................................................................................21 10/2010Revision 0: Initial Version Changes to High Performance ADC Driving Section and Figure 60..................................................................................24 Updated Outline Dimensions ......................................................25 Changes to Ordering Guide .........................................................25 Rev. D Page 2 of 25