Ultralow Distortion Differential ADC Driver Data Sheet ADA4937-1/ADA4937-2 FEATURES FUNCTIONAL BLOCK DIAGRAMS ADA4937-1 Extremely low harmonic distortion (HD) 112 dBc HD2 at 10 MHz 84 dBc HD2 at 70 MHz 77 dBc HD2 at 100 MHz FB 1 12 PD 102 dBc HD3 at 10 MHz +IN 2 11 OUT 91 dBc HD3 at 70 MHz IN 3 10 +OUT 84 dBc HD3 at 100 MHz 4 9 +FB V OCM Low input voltage noise: 2.2 nV/Hz High speed 3 dB bandwidth of 1.9 GHz, G = 1 Figure 1. ADA4937-1 Slew rate: 6000 V/s, 25% to 75% ADA4937-2 Fast overdrive recovery of 1 ns 0.5 mV typical offset voltage Externally adjustable gain Differential-to-differential or single-ended-to-differential 18 IN1 1 +OUT1 operation +FB1 2 17 V OCM1 Adjustable output common-mode voltage +V 3 16 V S1 S2 Single-supply operation: 3.3 V to 5 V 15 +V 4 V S1 S2 FB2 5 14 PD2 APPLICATIONS +IN2 6 13 OUT2 ADC drivers Single-ended-to-differential converters IF and baseband gain blocks Differential buffers Figure 2. ADA4937-2 Line drivers 55 HD2, V =5.0V S 60 HD3, V =5.0V S GENERAL DESCRIPTION HD2, V =3.3V S 65 HD3, V =3.3V S The ADA4937-1/ADA4937-2 are low noise, ultralow distortion, 70 high speed differential amplifiers. They are an ideal choice for 75 driving high performance ADCs with resolutions up to 16 bits 80 from dc to 100 MHz. The adjustable level of the output common 85 mode allows the ADA4937-1/ADA4937-2 to match the input 90 of the ADC. The internal common-mode feedback loop also 95 provides exceptional output balance as well as suppression of 100 even-order harmonic distortion products. 105 110 With the ADA4937-1/ADA4937-2, differential gain configurations 115 are easily realized with a simple external feedback network of 1 10 100 four resistors that determine the closed-loop gain of the amplifier. FREQUENCY (MHz) Figure 3. Harmonic Distortion vs. Frequency The ADA4937-1/ADA4937-2 are fabricated using Analog Devices, The ADA4937-1/ADA4937-2 are available in a Pb-free, 3 mm Inc., proprietary silicon-germanium (SiGe), complementary 3 mm, 16-lead LFCSP (ADA4937-1, single) or a Pb-free, 4 mm bipolar process, enabling them to achieve very low levels of 4 mm, 24-lead LFCSP (ADA4937-2, dual). The pinout has been distortion with an input voltage noise of only 2.2 nV/Hz. optimized to facilitate PCB layout and minimize distortion. The low dc offset and excellent dynamic performance of the The ADA4937-1/ADA4937-2 are specified to operate over the ADA4937-1/ADA4937-2 make them well-suited for a wide automotive (40C to +105C) temperature range and between variety of data acquisition and signal processing applications. 3.3 V and 5 V supplies. Rev. F Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20072016 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. DISTORTION (dBc) +V V S S +V V S S V +V S S +V V S S 06591-001 06591-002 06591-003 24 IN2 7 +IN1 5 16 +FB2 8 23 FB1 6 15 +V 9 22 V S2 S1 +V 10 21 V 7 14 S2 S1 20 V 11 PD1 OCM2 8 13 +OUT2 12 19 OUT1ADA4937-1/ADA4937-2 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Analyzing an Application Circuit ............................................ 18 Applications ....................................................................................... 1 Setting the Closed-Loop Gain .................................................. 18 General Description ......................................................................... 1 Estimating the Output Noise Voltage ...................................... 18 Functional Block Diagrams ............................................................. 1 Impact of Mismatches in the Feedback Networks ................. 19 Revision History ............................................................................... 2 Calculating the Input Impedance for an Application Circuit ....................................................................................................... 19 Specifications ..................................................................................... 3 Input Common-Mode Voltage Range in Single-Supply 5 V Operation ............................................................................... 3 Applications ................................................................................ 20 3.3 V Operation ............................................................................ 5 Setting the Output Common-Mode Voltage .......................... 20 Absolute Maximum Ratings ............................................................ 7 Power-Down Operation ............................................................ 20 Thermal Resistance ...................................................................... 7 Layout, Grounding, and Bypassing .............................................. 22 ESD Caution .................................................................................. 7 High Performance ADC Driving ................................................. 23 Pin Configurations and Function Descriptions ........................... 8 3.3 V Operation .......................................................................... 25 Typical Performance Characteristics ............................................. 9 Outline Dimensions ....................................................................... 26 Test Circuits ..................................................................................... 16 Ordering Guide .......................................................................... 26 Terminology .................................................................................... 17 Theory of Operation ...................................................................... 18 REVISION HISTORY 6/2016Rev. E to Rev. F Changes to Figure 5 and Figure 6 .................................................... 8 Added EP Row to Table 7 and EP Row to Table 8 ........................ 8 Updated Outline Dimensions ....................................................... 26 Changes to Ordering Guide .......................................................... 26 Added Figure 46, Figure 47, and Figure 48 Renumbered Sequentially ..................................................................................... 15 5/2015Rev. D to Rev. E Changes to Table 9 .......................................................................... 18 Changes to Table 6 ............................................................................ 7 Changes to Input Common-Mode Voltage Range in Single- Updated Outline Dimensions ....................................................... 26 Supply Applications Section .......................................................... 20 Changes to Ordering Guide .......................................................... 26 Changes to Ordering Guide .......................................................... 26 8/2013Rev. C to Rev. D 11/2007Rev. 0 to Rev. A Changes to Input Bias Current Parameter, Table 1 ...................... 3 Added the ADA4937-2 ...................................................... Universal Changes to Input Bias Current Parameter, Table 3 ...................... 5 Changes to Features .......................................................................... 1 Updated Outline Dimensions ....................................................... 26 Changes to Specifications ................................................................. 3 Changes to Figure 4 ........................................................................... 7 3/2010Rev. B to Rev. C Changes to Typical Performance Characteristics.......................... 9 Changes to Table 2, Power Supply Parameter ............................... 4 Inserted Figure 44 ........................................................................... 15 Changes to Table 4, Power Supply Parameter ............................... 6 Added the Terminating a Single-Ended Input Section ............. 19 Changes to Figure 43 ...................................................................... 15 Changes to Table 10 and Table 11 ................................................ 21 Added the Power-Down Operation Section ............................... 20 Changes to Layout, Grounding, and Bypassing Section ........... 22 Inserted Figure 59, Figure 60, and Figure 61 .............................. 22 10/2009Rev. A to Rev. B Updated Outline Dimensions ....................................................... 26 Changes to General Description Section ...................................... 1 Changes to Ordering Guide .......................................................... 26 Changes to Table 1 ............................................................................ 3 Changes to Operating Temperature Range Parameter, Table 2 .. 4 5/2007Revision 0: Initial Version Changes to Table 3 ............................................................................ 5 Changes to Figure 4 .......................................................................... 7 Rev. F Page 2 of 28