Ultralow Distortion, Differential ADC Driver Data Sheet ADA4939-1/ADA4939-2 FEATURES FUNCTIONAL BLOCK DIAGRAMS Extremely low harmonic distortion ADA4939-1 102 dBc HD2 at 10 MHz 83 dBc HD2 at 70 MHz 77 dBc HD2 at 100 MHz FB 1 12 PD 101 dBc HD3 at 10 MHz +IN 2 11 OUT 97 dBc HD3 at 70 MHz IN 3 10 +OUT 91 dBc HD3 at 100 MHz 49 +FB V OCM Low input voltage noise: 2.3 nV/Hz High speed 3 dB bandwidth of 1.4 GHz, G = 2 Slew rate: 6800 V/s, 25% to 75% Figure 1. ADA4939-1 Fast overdrive recovery of <1 ns 0.5 mV typical offset voltage Externally adjustable gain Stable for differential gains 2 IN1 1 18 +OUT1 Differential-to-differential or single-ended-to-differential +FB1 2 V 17 OCM1 +V V operation 3 16 S1 S2 ADA4939-2 +V V 4 15 S2 S1 Adjustable output common-mode voltage 5 FB2 14 PD2 Single-supply operation: 3.3 V to 5 V +IN2 6 13 OUT2 APPLICATIONS ADC drivers Single-ended-to-differential converters IF and baseband gain blocks Figure 2. ADA4939-2 Differential buffers The ADA4939-1 (single) is available in a 3 mm 3 mm, 16-lead Line drivers LFCSP, and the ADA4939-2 (dual) is available in a 4 mm 4 mm, GENERAL DESCRIPTION 24-lead LFCSP. The pinouts are optimized to facilitate printed The ADA4939-1/ADA4939-2 are low noise, ultralow distortion, circuit board (PCB) layout and minimize distortion. The high speed differential amplifiers. They are an ideal choice for ADA4939-1/ADA4939-2 are specified to operate over the driving high performance ADCs with resolutions up to 16 bits 40C to +105C temperature range both operate on supplies from dc to 100 MHz. The output common-mode voltage is user between 3.3 V and 5 V. adjustable by means of an internal common-mode feedback loop, 60 V = 2V p-p allowing the ADA4939-1/ADA4939-2 output to match the input OUT, dm 65 of the ADC. The internal feedback loop also provides exceptional HD2 HD3 70 output balance as well as suppression of even-order harmonic 75 distortion products. 80 With the ADA4939-1/ADA4939-2, differential gain configurations 85 are easily realized with a simple external feedback network of four resistors that determine the closed-loop gain of the amplifier. 90 The ADA4939-1/ADA4939-2 are fabricated using Analog Devices, 95 Inc., proprietary silicon-germanium (SiGe), complementary bipolar 100 process, enabling them to achieve very low levels of distortion with 105 an input voltage noise of only 2.3 nV/Hz. The low dc offset and 110 excellent dynamic performance of the ADA4939-1/ADA4939-2 1 10 100 FREQUENCY (MHz) make them well suited for a wide variety of data acquisition and signal processing applications. Figure 3. Harmonic Distortion vs. Frequency Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. 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HARMONIC DISTORTION (dBc) +V V S S +V V S S V +V S S +V V S S 07752-001 07429-002 07429-021 IN2 7 24 N1 +I 5 16 23 +FB2 8 FB1 6 15 +V 9 22 V S2 S1 +V 10 21 V 7 14 S2 S1 V 11 20 PD1 OCM2 8 13 19 +OUT2 12 OUT1ADA4939-1/ADA4939-2 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 17 Applications ....................................................................................... 1 Analyzing an Application Circuit ............................................ 17 General Description ......................................................................... 1 Setting the Closed-Loop Gain .................................................. 17 Functional Block Diagrams ............................................................. 1 Stable for Gains 2 ..................................................................... 17 Revision History ............................................................................... 2 Estimating the Output Noise Voltage ...................................... 17 Specif icat ions ..................................................................................... 3 Impact of Mismatches in the Feedback Networks ................. 18 5 V Operation ............................................................................... 3 Calculating the Input Impedance for an Application Circuit ....................................................................................................... 19 3.3 V Operation ............................................................................ 5 Input Common-Mode Voltage Range ..................................... 21 Absolute Maximum Ratings ............................................................ 7 Input and Output Capacitive AC Coupling ............................ 21 Thermal Resistance ...................................................................... 7 Minimum RG Value of 50 ...................................................... 21 Maximum Power Dissipation ..................................................... 7 Setting the Output Common-Mode Voltage .......................... 21 ESD Caution .................................................................................. 7 Layout, Grounding, and Bypassing .............................................. 22 Pin Configurations and Function Descriptions ........................... 8 High Performance ADC Driving ................................................. 23 Typical Performance Characteristics ............................................. 9 Outline Dimensions ....................................................................... 24 Test Circuits ..................................................................................... 15 Ordering Guide .......................................................................... 24 Operational Description ................................................................ 16 Definition of Terms .................................................................... 16 REVISION HISTORY 5/2016Rev. 0 to Rev. A Changed ADA4939 to ADA4939-1/ADA4939-2, CP-16-2 to CP-16-21, and CP-24-1 to CP-24-10 ........................... Throughout Changes to Figure 5, Figure 6, Table 9, and Table 10 ................... 8 Changes to Figure 54 ...................................................................... 23 Updated Outline Dimensions ....................................................... 24 Changes to Ordering Guide .......................................................... 24 5/2008Revision 0: Initial Version Rev. A Page 2 of 24