Low Power, Selectable Gain Differential ADC Driver, G = 1, 2, 3 Data Sheet ADA4950-1/ADA4950-2 FEATURES FUNCTIONAL BLOCK DIAGRAMS ADA4950-1 High performance at low power High speed 3 dB bandwidth of 750 MHz, G = 1 0.1 dB flatness to 210 MHz, V = 2 V p-p, R = 200 OUT, dm L, dm +INB 1 12 PD Slew rate: 2900 V/s, 25% to 75% +INA 2 11 OUT Fast 0.1% settling time of 9 ns INA 3 10 +OUT Low power: 9.5 mA per amplifier INB 4 9 V OCM Low harmonic distortion 108 dB SFDR 10 MHz 98 dB SFDR 20 MHz Low output voltage noise: 9.2 nV/Hz, G = 1, RTO Figure 1. ADA4950-1 0.2 mV typical input offset voltage ADA4950-2 Selectable differential gains of 1, 2, and 3 Differential-to-differential or single-ended-to-differential operation Adjustable output common-mode voltage INA1 1 18 +OUT1 Input common-mode range shifted down by 1 V BE INB1 2 17 V OCM1 Wide supply range: +3 V to 5 V 16 +V 3 V S1 S2 +V 15 V 4 Available in 16-lead and 24-lead LFCSP packages S1 S2 +INB2 5 14 PD2 APPLICATIONS +INA2 6 13 OUT2 ADC drivers Single-ended-to-differential converters IF and baseband gain blocks Differential buffers Figure 2. ADA4950-2 Line drivers 40 V = 2V p-p OUT, dm GENERAL DESCRIPTION 50 60 The ADA4950-1/ADA4950-2 are gain-selectable versions of the HD2, 5V HD3, 5V ADA4932-1/ADA4932-2 with on-chip feedback and gain resistors. 70 HD2, 2.5V HD3, 2.5V They are ideal choices for driving high performance ADCs as single- 80 ended-to-differential or differential-to-differential amplifiers. The 90 output common-mode voltage is user adjustable by means of an 100 internal common-mode feedback loop, allowing the ADA4950-1/ 110 ADA4950-2 output to match the input of the ADC. The internal 120 feedback loop also provides exceptional output balance as well as suppression of even-order harmonic distortion products. 130 140 Differential gain configurations of 1, 2, and 3 are easily realized 0.1 1 10 100 with internal feedback networks that are connected externally FREQUENCY (MHz) to set the closed-loop gain of the amplifier. Figure 3. Harmonic Distortion vs. Frequency at Various Supplies The ADA4950-1/ADA4950-2 are fabricated using the Analog The devices are available in a Pb-free, 3 mm 3 mm, 16-lead Devices, Inc., proprietary silicon-germanium (SiGe) complementary LFCSP (ADA4950-1, single) or a Pb-free, 4 mm 4 mm, 24-lead bipolar process, enabling them to achieve low levels of distortion and LFCSP (ADA4950-2, dual). The pinout has been optimized to noise at low power consumption. The low offset and excellent facilitate PCB layout and minimize distortion. The ADA4950-1/ dynamic performance of the ADA4950-x make it well suited for ADA4950-2 are specified to operate over the 40C to +105C a wide variety of data acquisition and signal processing applications. temperature range both operate on supplies from +3 V to 5 V. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20092015 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. 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Technical Support www.analog.com HARMONIC DISTORTION (dBc) 07957-001 07957-002 07957-025 INA2 7 24 +INA1 +V 5 16 V S S INB2 23 8 +INB1 +V 6 15 V S S +V 9 22 V S2 S1 +V 7 14 V S S 21 +V 10 V S2 S1 +V 8 13 V S S V 11 20 PD1 OCM2 +OUT2 12 19 OUT1ADA4950-1/ADA4950-2 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 18 Applications ....................................................................................... 1 Applications Information .............................................................. 19 General Description ......................................................................... 1 Analyzing an Application Circuit ............................................ 19 Functional Block Diagrams ............................................................. 1 Selecting the Closed-Loop Gain ............................................... 19 Revision History ............................................................................... 2 Estimating the Output Noise Voltage ...................................... 19 Specifications ..................................................................................... 3 Calculating the Input Impedance for an Application Circuit .......................................................................................... 20 5 V Operation ............................................................................. 3 Input Common-Mode Voltage Range ..................................... 22 5 V Operation ............................................................................... 5 Input and Output Capacitive AC Coupling ............................ 22 Absolute Maximum Ratings ............................................................ 7 Input Signal Swing Considerations .......................................... 22 Thermal Resistance ...................................................................... 7 Setting the Output Common-Mode Voltage .......................... 22 Maximum Power Dissipation ..................................................... 7 Layout, Grounding, and Bypassing .............................................. 23 ESD Caution .................................................................................. 7 High Performance ADC Driving ................................................. 24 Pin Configurations and Function Descriptions ........................... 8 Outline Dimensions ....................................................................... 25 Typical Performance Characteristics ............................................. 9 Ordering Guide .......................................................................... 25 Test Circuits ..................................................................................... 16 Terminology .................................................................................... 17 REVISION HISTORY 10/15Rev. A to Rev. B Changed CP-16-2 to CP-16-21 ......................................... Universal Changes to Figure 1 .......................................................................... 1 Changes to Figure 5 .......................................................................... 8 Updated Outline Dimensions ....................................................... 25 Changes to Ordering Guide .......................................................... 25 3/13Rev. 0 to Rev. A Updated Outline Dimensions ....................................................... 25 Changes to Ordering Guide .......................................................... 25 5/09Revision 0: Initial Version Rev. B Page 2 of 26