Low Distortion, 3.2 GHz, RF DGA Data Sheet ADA4961 FEATURES FUNCTIONAL BLOCK DIAGRAM High speed 3 dB bandwidth: 3.2 GHz 24 23 22 21 20 19 1 dB bandwidth: 1.8 GHz EXPOSED ADA4961 Slew rate: 12,000 V/s PAD Digitally adjustable gain 2 17 VIN+ VOUT+ 0dB TO 21dB Voltage gain: 6 dB to +15 dB ATTEN +15dB Power gain: 3 dB to +18 dB VIN 3 16 VOUT 5-bit parallel or SPI bus gain control with fast attack 18 DNC GND 4 15 IMD3/HD3 distortion, maximum gain, 5 V, high performance DNC 5 GND 14 DNC (HP) mode 1 7 8 9 10 11 12 13 6 IMD3/HD3 at 1 GHz: 90 dBc/83 dBc IMD3/HD3 at 1.5 GHz: 85 dBc/75 dBc IMD3/HD3 at 2 GHz: 70 dBc/70 dBc NOTES Low noise 1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN. Noise density referred to output (RTO): 154 dBm/Hz Figure 1. Noise figure: 5.5 dB at A = 15 dB, 1 GHz V Differential impedances: 100 input, 50 output Low power mode operation, power-down control Single 3.3 V or 5 V supply operation Available in 24-lead, 4 mm 4 mm LFCSP APPLICATIONS ADC driver for 10-bit to 14-bit GSPS converters RF/IF gain blocks Line drivers Instrumentation Satellite communications Data acquisition Military systems GENERAL DESCRIPTION The ADA4961 is a high performance, BiCMOS RF digital gain digital adjustability provides for 1 dB resolution, thus optimizing amplifier (DGA), optimized for driving heavy loads out to the signal-to-noise ratio (SNR) for input levels spanning 21 dB. 2.0 GHz and beyond. The device typically achieves 90 dBc The ADA4961 is optimized for wideband, low distortion IMD3 performance at 500 MHz and 85 dBc at 1.5 GHz. This performance at frequencies up to 2 GHz. These attributes, RF performance allows GHz converters to achieve their optimum together with wide gain adjustment and relatively low power, performance with minimal limitations of the driver amplifier or make the ADA4961 the amplifier of choice for many high speed constraints on overall power that typically result from GaAs applications, including IF, RF, and broadband applications amplifiers. This device can easily drive 10-bit to16-bit HS where dynamic range at very high frequencies is critical. converters. The ADA4961 is ideally suited for driving not only analog-to- For many receiver applications, antialias filter (AAF) designs digital converters (ADCs), but also mixers, pin diode attenuators, can be simplified or not required. SAW filters, and multielement discrete devices. It is available in The ADA4961 has an internal differential input impedance of a 4 mm 4 mm, 24-lead LFCSP and operates over a 100 and a differential dynamic output impedance of 50 , temperature range of 40C to +85C. eliminating the need for external termination resistors. The Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20142019 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. GND VCC4 SDIO VCC3 A4/CLK VCC2 A3/CS VCC1 A2/FA A1 A0 PM LATCH PWUP MODE 12454-001ADA4961 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 AC Characterization Output Filter .......................................... 15 Applications ....................................................................................... 1 Theory of Operation ...................................................................... 16 Functional Block Diagram .............................................................. 1 Digital Interface Overview ........................................................ 16 General Description ......................................................................... 1 Parallel Digital Interface ............................................................ 16 Revision History ............................................................................... 2 Serial Peripheral Interface (SPI) ............................................... 16 Specif icat ions ..................................................................................... 3 Applications Information .............................................................. 17 Noise/Harmonic Performance .................................................... 4 Basic Connections ...................................................................... 17 Timing Specifications .................................................................. 5 ADC Driving ............................................................................... 18 Absolute Maximum Ratings ............................................................ 6 Low-Pass Antialias Filtering for the ADC Interface .............. 20 Thermal Resistance ...................................................................... 6 Layout Considerations ............................................................... 21 ESD Caution .................................................................................. 6 Evaluation Board ........................................................................ 21 Pin Configuration and Function Descriptions ............................. 7 Outline Dimensions ....................................................................... 24 Typical Performance Characteristics ............................................. 8 Ordering Guide .......................................................................... 24 Characterization and Test Circuits ............................................... 14 REVISION HISTORY 7/2019Rev. B to Rev. C 10/2014Revision 0: Initial Version Replaced Figure 11 ........................................................................... 9 3/2019Rev. A to Rev. B Changes to Figure 45 ...................................................................... 20 Updated Outline Dimension ......................................................... 24 Changes to Ordering Guide .......................................................... 24 12/2014Rev. 0 to Rev. A Changes to Features Section............................................................ 1 Changes to Table 2 ............................................................................ 4 Changes to Pin 13, Table 6............................................................... 7 Added Figure 33 Renumbered Sequentially .............................. 12 Added Figure 34 and Figure 35..................................................... 13 Changes to Table 10 ........................................................................ 17 Changes to Figure 52 ...................................................................... 23 Rev. C Page 2 of 24