SigmaDSP Digital Audio Processor with Flexible Audio Routing Matrix Data Sheet ADAU1442/ADAU1445/ADAU1446 2 FEATURES I C and SPI control interfaces Standalone operation Fully programmable audio digital signal processor (DSP) for Self-boot from serial EEPROM enhanced sound processing 4-channel, 10-bit auxiliary control ADC Features SigmaStudio, a proprietary graphical programming Multipurpose pins for digital controls and outputs tool for the development of custom signal flows Easy implementation of available third-party algorithms 172 MHz SigmaDSP core 3584 instructions per sample at 48 kHz On-chip regulator for generating 1.8 V from 3.3 V supply 4k parameter RAM, 8k data RAM 100-lead TQFP and LQFP packages Flexible audio routing matrix (FARM) Temperature range: 40C to +105C 24-channel digital input and output Up to 8 stereo asynchronous sample rate converters APPLICATIONS (from 1:8 up to 7.75:1 ratio and 139 dB DNR) Automotive audio processing Stereo S/PDIF input and output Head units Supports serial and TDM I/O, up to f = 192 kHz S Navigation systems Multichannel byte-addressable TDM serial port Rear-seat entertainment systems Pool of 170 ms digital audio delay (at 48 kHz) DSP amplifiers (sound system amplifiers) Clock oscillator for generating master clock from crystal Commercial audio processing PLL for generating core clock from common audio clocks FUNCTIONAL BLOCK DIAGRAM MP 3:0 / 2 SPI/I C* SELFBOOT MP 11:4 ADC 3:0 XTALI XTALO ADAU1442/ ADAU1445/ ADAU1446 2 I C/SPI CONTROL MP/ CLOCK INTERFACE CLKOUT AUX ADC PLL OSCILLATOR AND SELF-BOOT 1.8V REGULATOR PROGRAMMABLE AUDIO S/PDIF S/PDIF SPDIFI SPDIFO PROCESSOR CORE RECEIVER TRANSMITTER FLEXIBLE AUDIO ROUTING MATRIX (FARM) SDATA IN 8:0 SDATA OUT 8:0 (24-CHANNEL (24-CHANNEL SERIAL DATA SERIAL DATA DIGITAL AUDIO UP TO 16 CHANNELS OF DIGITAL AUDIO INPUT PORT OUTPUT PORT INPUT) (9) OUTPUT) (9) ASYNCHRONOUS SAMPLE RATE CONVERTERS BIT CLOCK BIT CLOCK (BCLK) (BCLK) SERIAL CLOCK DOMAINS (12) FRAME CLOCK FRAME CLOCK (LRCLK) (LRCLK) 2 *SPI/I C = THE ADDR0, CLATCH, SCL/CCLK, SDA/COUT, AND ADDR1/CDATA PINS. THERE ARE 12 BIT CLOCKS (BCLK 11:0 ) AND 12 FRAME CLOCKS (LRCLK 11:0 ) IN TOTAL. OF THE 12 CLOCKS, SIX ARE ASSIGNABLE, THREE MUST BE OUTPUTS, AND THREE MUST BE INPUTS. Figure 1. Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20102013 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 07696-001ADAU1442/ADAU1445/ADAU1446 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 ASRC Modes and Settings ........................................................ 58 Applications ....................................................................................... 1 DSP Core ..................................................................................... 60 Functional Block Diagram .............................................................. 1 DSP Core Modes and Settings .................................................. 61 Revision History ............................................................................... 3 Reliability Features ..................................................................... 62 General Description ......................................................................... 4 RAMs ........................................................................................... 64 Specifications ..................................................................................... 5 S/PDIF Receiver and Transmitter ............................................ 65 Digital Timing Specifications ..................................................... 8 S/PDIF Modes and Settings ...................................................... 66 Absolute Maximum Ratings .......................................................... 11 Multipurpose Pins ...................................................................... 69 Thermal Resistance .................................................................... 11 Multipurpose Pins Modes and Settings................................... 69 ESD Caution ................................................................................ 11 Auxiliary ADC ............................................................................ 70 Pin Configuration and Function Descriptions ........................... 12 Auxiliary ADC Modes and Settings ........................................ 70 Theory of Operation ...................................................................... 17 Interfacing with Other Devices .................................................... 71 System Block Diagram ............................................................... 17 Drive Strength Modes and Settings ......................................... 71 Overview ...................................................................................... 18 Flexible TDM Modes ..................................................................... 76 Initialization ................................................................................ 20 Serial Input Flexible TDM Interface Modes and Settings..... 76 Master Clock and PLL ............................................................... 21 Serial Output Flexible TDM Interface Modes and Settings . 78 Voltage Regulator ....................................................................... 25 Software Features ............................................................................ 81 SRC Group Delay ....................................................................... 25 Software Safeload ....................................................................... 81 Control Port ................................................................................ 26 Software Slew .............................................................................. 81 Serial Data Input/Output........................................................... 31 Global RAM and Register Map .................................................... 82 Serial Input Ports ........................................................................ 37 Overview of Register Address Map ......................................... 82 Serial Input Port Modes and Settings ...................................... 39 Details of Register Address Map .............................................. 82 Serial Output Ports ..................................................................... 41 Applications Information .............................................................. 87 Serial Output Port Modes and Settings ................................... 42 Layout Recommendations ........................................................ 87 Flexible Audio Routing Matrix (FARM) ................................. 46 Typical Application Schematics ................................................ 89 Flexible Audio Routing Matrix Modes and Settings.............. 52 Outline Dimensions ....................................................................... 92 Asynchronous Sample Rate Converters .................................. 58 Ordering Guide .......................................................................... 92 Rev. D Page 2 of 92