SigmaDSP Digital Audio Processor Data Sheet ADAU1463/ADAU1467 FEATURES Clock oscillator for generating master clock from crystal Integer PLL and flexible clock generators Qualified for automotive applications Integrated die temperature sensor Fully programmable audio DSP for enhanced sound processing 2 I C and SPI control interfaces (both slave and master) Features SigmaStudio, a proprietary graphical programming Standalone operation tool for the development of custom signal flows Self boot from serial EEPROM Up to 294.912 MHz, 32-bit SigmaDSP core at 1.2 V 8-channel, 10-bit SAR auxiliary control ADC Up to 24 kWords of program memory 26 multipurpose pins for digital controls and outputs Up to 80 kWords of parameter/data RAM On-chip regulator for generating 1.2 V from 3.3 V supply Up to 6144 SIMD instructions per sample at 48 kHz 88-lead, 12 mm 12 mm LFCSP package with 5.3 mm Up to 1600 ms digital audio delay pool at 48 kHz exposed pad Audio I/O and routing Temperature range: 40C to +105C 4 serial input ports, 4 serial output ports 48-channel, 32-bit digital I/O up to a sample rate of 192 kHz APPLICATIONS 2 Flexible configuration for TDM, I S, left and right justified Automotive audio processing formats, and PCM Head units 8 stereo ASRCs from 1:8 up to 7.75:1 ratio and Distributed amplifiers 139 dB dynamic range Rear seat entertainment systems Stereo S/PDIF input and output at 192 kHz Trunk amplifiers 4 PDM microphone input channels Commercial and professional audio processing Multichannel, byte addressable TDM serial ports FUNCTIONAL BLOCK DIAGRAM 2 2 SPI/I C* SPI/I C* PLLFILT ADAU1467/ ADAU1463 VDRIVE REGULATOR 2 2 GPIO/ I C/SPI I C/SPI CLOCK CLKOUT PLL AUX ADC OSCILLATOR SLAVE MASTER THD P TEMPERATURE SENSOR THD M INPUT AUDIO OUTPUT AUDIO ROUTING MATRIX ROUTING MATRIX S/PDIF S/PDIF SPDIFIN SPDIFOUT RECEIVER TRANSMITTER 2 294.912MHz PROGRAMMABLE DIGITAL AUDIO PROCESSING CORE (48-CHANNEL MIC INPUT DIGITAL AUDIO INPUTS) RAM, ROM, WATCHDOG, MEMORY PARITY CHECK SERIAL DATA (48-CHANNEL OUTPUT PORTS SERIAL DATA DIGITAL AUDIO (4) INPUT PORTS SDATA OUT3 TO SDATA OUT0 INPUTS) (4) 8 2-CHANNEL ASYNCHRONOUS SAMPLE RATE CONVERTERS SERIAL DATA PORTS, SELECTABLE INPUT/OUTPUT (x8) SDATAIO7 TO SDATAIO0 SDATAIO7 TO SDATAIO0 INPUT OUTPUT BCLK OUT3 TO BCLK OUT0/ BCLK IN3 TO BCLK IN0/ CLOCK CLOCK LRCLK IN3 TO LRCLK IN0 LRCLK OUT3 TO LRCLK OUT0 DEJITTER AND DOMAINS DOMAINS (OUTPUT CLOCK PAIRS) (INPUT CLOCK PAIRS) CLOCK GENERATOR (4) (4) 2 *SPI/I C INCLUDES THE FOLLOWING PIN FUNCTIONS: SS M, MOSI M, SCL M, SCLK M, SDA M, MISO M, MISO, SDA, SCLK, SCL, MOSI, ADDR1, SS, AND ADDR0 PINS. Figure 1. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 2018 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. SELFBOOT MP25 TO MP0 AUXADC7 TO AUXADC0 XTALIN/MCLK XTALOUT 14809-001ADAU1463/ADAU1467 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Random Access Memory .......................................................... 90 Applications ....................................................................................... 1 Control Registers ........................................................................ 93 Functional Block Diagram .............................................................. 1 Control Register Details ................................................................ 99 Revision History ............................................................................... 3 PLL Configuration Registers .................................................... 99 General Description ......................................................................... 4 Clock Generator Registers ...................................................... 103 Differences Between the ADAU1463 and ADAU1467 ........... 4 Power Reduction Registers ..................................................... 109 Specifications ..................................................................................... 5 Slave Control Port Memory Page Setting Register .............. 111 Electrical Characteristics ............................................................. 7 Audio Signal Routing Registers .............................................. 112 Timing Specifications .................................................................. 9 Serial Port Configuration Registers ....................................... 120 Absolute Maximum Ratings .......................................................... 17 SDATA Port Routing Register ................................................ 123 Thermal Considerations ............................................................ 17 Flexible TDM Interface Registers ........................................... 125 ESD Caution ................................................................................ 17 DSP Core Control Registers .................................................... 128 Pin Configuration and Function Descriptions ........................... 18 Debug and Reliability Registers .............................................. 133 Theory of Operation ...................................................................... 24 DSP Program Execution Registers ......................................... 141 System Block Diagram ............................................................... 24 Panic Mask Registers ............................................................... 144 Overview ...................................................................................... 24 Multipurpose Pin Configuration Registers........................... 157 Initialization ................................................................................ 26 ASRC Status and Control Registers ....................................... 162 Master Clock, PLL, and Clock Generators.............................. 30 Auxiliary ADC Registers ......................................................... 166 2 Power Supplies, Voltage Regulator, and Hardware Reset ...... 35 Secondary I C Master Register ............................................... 166 Temperature Sensor Diode........................................................ 36 S/PDIF Interface Registers ...................................................... 167 Slave Control Ports ..................................................................... 36 S/PDIF Receiver MCLK Speed Selection Register ............... 170 Slave Control Port Addressing .................................................. 37 S/PDIF Transmitter MCLK Speed Selection Register ......... 171 Slave Port to DSP Core Address Mapping .............................. 37 Hardware Interfacing Registers .............................................. 179 Master Control Ports .................................................................. 44 MP14 Pin Drive Strength and Slew Rate Register ............... 197 Self Boot ....................................................................................... 45 MP15 Pin Drive Strength and Slew Rate Register ............... 198 Serial Data Input/Output........................................................... 46 SDATA In/Out Pins Drive Strength and Slew Rate Registers ..................................................................................................... 199 SDATAIOx Pins .......................................................................... 53 MP24 Pin Drive Strength and Slew Rate Register ............... 200 Serial Clock Domains ................................................................ 54 MP25 Pin Drive Strength and Slew Rate Register ............... 201 Asynchronous Sample Rate Converters .................................. 63 Soft Reset Register .................................................................... 202 Audio Signal Routing ................................................................. 67 Applications Information ............................................................ 203 Flexible TDM Interface .............................................................. 69 PCB Design Considerations ................................................... 203 S/PDIF Interface ......................................................................... 74 Typical Applications Block Diagram ..................................... 204 Digital PDM Microphone Interface ......................................... 77 Example PCB Layout ............................................................... 205 Multipurpose Pins ...................................................................... 78 PCB Manufacturing Guidelines ............................................. 206 Auxiliary ADC ............................................................................ 82 Outline Dimensions ..................................................................... 207 SigmaDSP Core .......................................................................... 82 Ordering Guide ........................................................................ 207 Software Features ........................................................................ 87 Automotive Products ............................................................... 207 Pin Drive Strength, Slew Rate, and Pull Configuration ........ 88 Global RAM and Control Register Map ...................................... 90 Rev. A Page 2 of 207