Quad Analog-to-Digital Converter (ADC) Data Sheet ADAU1978 FEATURES GENERAL DESCRIPTION Four 2 V rms differential inputs The ADAU1978 incorporates four high performance, analog-to- On-chip phase-locked loop (PLL) for master clock digital converters (ADCs) with 2 V rms capable ac-coupled inputs. Low electromagnetic interference (EMI) design The ADCs use a multibit sigma-delta (-) architecture with 2 109 dB analog-to-digital converter (ADC) dynamic range continuous time front end for low EMI. An I C/serial peripheral Total harmonic distortion + noise (THD + N): 95 dB interface (SPI) control port is included that allows a microcontroller Selectable digital high-pass filter to adjust volume and many other parameters. The ADAU1978 24-bit stereo ADC with 8 kHz to 192 kHz sample rates uses only a single 3.3 V supply. The part internally generates the Digital volume control with autoramp function required digital DVDD supply. The low power architecture 2 I C/SPI controllable for flexibility reduces the power consumption. The ADAU1978 is available in Software-controllable clickless mute a 40-lead LFCSP package. The on-chip PLL can derive the master Software power-down clock from an external clock input or frame clock (sample rate 2 Right justified, left justified, I S, and TDM modes clock). When fed with the frame clock, it eliminates the need Master and slave operation modes for a separate high frequency master clock in the system. 40-lead LFCSP package Note that throughout this data sheet, multifunction pins, such Qualified for automotive applications as SCL/CCLK, are referred to either by the entire pin name or by a single function of the pin, for example, CCLK, when only APPLICATIONS that function is relevant. Automotive audio systems Active noise cancellation systems FUNCTIONAL BLOCK DIAGRAM 3.3V TO 1.8V DVDD REGULATOR ADAU1978 AIN1P ADC IOVDD AIN1N LRCLK AIN2P ADC AIN2N BCLK AIN3P ADC SDATAOUT1 AIN3N AIN4P ADC SDATAOUT2 AIN4N AGND1 AGND3 SCL/CCLK SDA/COUT AVDD2 2 ADDR1/CIN I C/SPI BG CONTROL PLL ADDR0/CLATCH REF PD/RST AGND2 AGND2 Figure 1. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20132014 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com AGND1 AGND2 AGND3 AGND4 AGND5 AGND6 DGND VREF AVDD1 AVDD1 MCLKIN AVDD3 AVDD3 AVDD2 PROGRAMMABLE GAIN PLL FILT DECIMATOR/HPF DC CALIBRATION SA MODE SERIAL AUDIO PORT 11292-001ADAU1978 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 SPI Mode ..................................................................................... 25 Applications ....................................................................................... 1 Register Summary .......................................................................... 27 General Description ......................................................................... 1 Register Details ............................................................................... 28 Functional Block Diagram .............................................................. 1 Master Power and Soft Reset Register ..................................... 28 Revision History ............................................................................... 2 PLL Control Register ................................................................. 29 Specifications ..................................................................................... 3 Block Power Control and Serial Port Control Register ......... 30 Analog Performance Specifications ........................................... 3 Serial Port Control Register 1 ................................................... 31 Digital Input/Output Specifications........................................... 3 Serial Port Control Register 2 ................................................... 32 Power Supply Specifications........................................................ 4 Channel 1 and Channel 2 Mapping for Output Serial Ports Register ........................................................................................ 33 Digital Filter Specifications ......................................................... 4 Channel 3 and Channel 4 Mapping for Output Serial Ports Timing Specifications .................................................................. 5 Register ........................................................................................ 35 Absolute Maximum Ratings ............................................................ 7 Serial Output Drive and Overtemperature Protection Control Thermal Resistance ...................................................................... 7 Register ........................................................................................ 36 ESD Caution .................................................................................. 7 Post ADC Gain Channel 1 Control Register .......................... 37 Pin Configuration and Function Descriptions ............................. 8 Post ADC Gain Channel 2 Control Register .......................... 38 Typical Performance Characteristics ........................................... 10 Post ADC Gain Channel 3 Control Register .......................... 38 Theory of Operation ...................................................................... 12 Post ADC Gain Channel 4 Control Register .......................... 39 Overview ...................................................................................... 12 High-Pass Filter and DC Offset Control Register and Master Power Supply and Voltage Reference ....................................... 12 Mute Register .............................................................................. 40 Power-On Reset Sequence ........................................................ 12 ADC Clipping Status Register .................................................. 41 PLL and Clock ............................................................................. 13 Digital DC High-Pass Filter and Calibration Register .......... 42 Analog Inputs .............................................................................. 14 Typical Application Circuit ........................................................... 43 ADC ............................................................................................. 16 Outline Dimensions ....................................................................... 44 ADC Summing Modes .............................................................. 16 Ordering Guide .......................................................................... 44 Serial Audio Data Output Ports, Data Format ....................... 17 Automotive Products ................................................................. 44 Control Ports ................................................................................... 21 2 I C Mode ...................................................................................... 22 REVISION HISTORY 1/14Rev. 0 to Rev. A Change to Features Section ............................................................. 1 Change to Dynamic Range (A-Weighted) Line Input Parameter, Table 1 ............................................................................. 3 Change to Figure 9 ......................................................................... 10 Change to Figure 34 ....................................................................... 23 Changes to Figure 44 ...................................................................... 43 5/13Revision 0: Initial Version Rev. A Page 2 of 44