ADAU7002ACBZ-R7 Analog Devices

2 Stereo PDM-to-I S or TDM Conversion IC Data Sheet ADAU7002 FEATURES GENERAL DESCRIPTION 64 decimation of a stereo pulse density modulation (PDM) The ADAU7002 converts a stereo PDM bit stream into a PCM bit stream to pulse code modulation (PCM) audio data output. The source for the PDM data can be two microphones 2 Slave I S or time division multiplexed (TDM) output interface or other PDM sources. The PCM audio data is output on a 2 Configurable TDM slots serial audio interface port in either I S or TDM format. I/O supply operation: 1.62 V to 3.6 V The ADAU7002 is specified over the commercial temperature 64 output sample rate PDM clock range (40C to +85C). It is available in a halide-free, 8-ball, 64/128/192/256/384/512 output sample rate BCLK 1.56 mm 0.76 mm, wafer level chip scale package (WLCSP). Automatic BCLK ratio detection Output sample rate: 4 kHz to 96 kHz Automatic PDM CLK drive at 64 the sample rate Automatic power down with BCLK removal 0.67 mA operating current at 48 kHz and 1.8 V IOVDD supply Shutdown current: <1 A 8-ball, 1.56 mm 0.76 mm, 0.4 mm pitch WLCSP Power-on reset APPLICATIONS Mobile computing Portable electronics Consumer electronics FUNCTIONAL BLOCK DIAGRAM 1.62V TO 3.6V CONFIG GND IOVDD PDM CLK BCLK 2 PDM DIGITAL I S INPUT DECIMATION OUTPUT LRCLK PORT FILTERING PORT PDM DAT SDATA ADAU7002 Figure 1. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20132019 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com 11265-001ADAU7002 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Pin Configuration and Function Descriptions ..............................5 Applications ....................................................................................... 1 Typical Performance Characteristics ..............................................6 General Description ......................................................................... 1 Typical Application Circuit ..............................................................8 Functional Block Diagram .............................................................. 1 Applications Information .................................................................9 Revision History ............................................................................... 2 Overview ........................................................................................9 Specifications ..................................................................................... 3 Clocking..........................................................................................9 Absolute Maximum Ratings ............................................................ 4 Serial Audio Output Interface .....................................................9 Thermal Resistance ...................................................................... 4 Outline Dimensions ....................................................................... 13 ESD Caution .................................................................................. 4 Ordering Guide .......................................................................... 13 REVISION HISTORY 7/2013Rev. 0 to Rev. A 11/2019Rev. B to Rev. C Changes to Supply Current Test Conditions/Comments ............ 3 Changes to Figure 12 ........................................................................ 9 Changes to Figure 5 ........................................................................... 6 Added Figure 6 Renumbered Sequentially ................................... 6 11/2016Rev. A to Rev. B Changes to Figure 14 and Figure 15 ............................................ 10 Change to Serial Port Timing Section and Time From BCLK Changes to Figure 16, Figure 17, and Figure 18 ......................... 11 Falling Parameter Table 7 ............................................................. 10 Changes to Figure 19, Figure 20, and Figure 21 ......................... 12 Changes to Figure 19 Caption and Figure 21 Caption .............. 12 1/2013Revision 0: Initial Version Rev. C Page 2 of 16