Audio Processor for Advanced TV with Sound IF Demodulator and Stereo Decoder ADAV4622 FEATURES PRODUCT OVERVIEW Sound IF (SIF) processor The ADAV4622 is an enhanced audio processor targeting SIF demodulator and broadcast stereo decoder advanced TV applications with full support for digital and NICAM (BG, DK, I, L), A2 (BG, DK, M), BTSC (M, N), EIAJ (M) analog baseband audio as well as multistandard broadcast SIF Automatic sound IF standard detection demodulation and decoding. Fully programmable 28-bit audio processor for enhanced The audio processor, by default, loads a dedicated TV audio ATV sounddefault TV audio flow loaded on reset flow that incorporates full matrix switching (any input to any Implements Analog Devices and third-party branded audio output), automatic volume control that compensates for volume algorithms changes during advertisements or when switching channels, Adjustable digital delay line for audio/video dynamic bass, a multiband equalizer, and up to 200 ms of stereo Synchronization for up to 200 ms stereo delay delay memory for audio-video synchronization. High performance 24-bit ADC and DAC Alternatively, Analog Devices, Inc., offers an award-winning 94 dB DNR performance on DAC channels graphical programming tool (SigmaStudio) that allows custom 95 dB DNR performance on ADC channels flows to be quickly developed and evaluated. This allows the Dual headphone outputs with integrated amplifiers creation of customer-specific audio flows, including use of the High performance pulse-width modulation (PWM) digital Analog Devices library of third-party algorithms. outputs Multichannel digital baseband I/O The analog I/O integrates Analog Devices proprietary 2 4 stereo synchronous digital I S input channels continuous-time, multibit - architecture to bring a higher One 6-channel sample rate converter (SRC) and one level of performance to ATV systems, required by third-party stereo SRC supporting input sample rates from algorithm providers to meet system branding certification. The 5 kHz to 50 kHz analog input is provided by 95 dB dynamic range (DNR) ADCs, 2 One stereo synchronous digital I S output and analog output is provided by 94 dB DNR DACs. S/PDIF output with S/PDIF input mux capability The main speaker outputs can be supplied as a digitally 2 Fast I C control modulated PWM stream to support digital amplifiers. Operates from 3.3 V (analog), 1.8 V (digital core), and 3.3 V The ADAV4622 includes multichannel digital inputs and (digital interface) outputs. In addition, digital input channels can be routed Available in 80-lead LQFP through integrated sample rate converters (SRC), which are capable of supporting any arbitrary sample rate from 5 kHz APPLICATIONS to 50 kHz. General-purpose consumer audio postprocessing Home audio DVD recorders Home theater in a box (HTIB) systems and DVD receivers Audio processing subsystems for DTV-ready TVs Analog broadcast capability for iDTVs Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 20082009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. ADAV4622 TABLE OF CONTENTS Features .............................................................................................. 1 VREF ............................................................................................ 20 Applications ....................................................................................... 1 FILTA and FILTD ....................................................................... 20 Product Overview ............................................................................. 1 PWM1A, PWM1B, PWM2A, PWM2B, PWM3A, PWM3B, PWM4A, and PWM4B .............................................................. 20 Revision History ............................................................................... 2 PWM READY ........................................................................... 20 Functional Block Diagram .............................................................. 3 AVDD .......................................................................................... 20 Specif icat ions ..................................................................................... 4 DVDD .......................................................................................... 20 Performance Parameters ............................................................. 4 ODVDD ....................................................................................... 20 Timing Specifications .................................................................. 9 D GND .......................................................................................... 20 Timing Diagrams ........................................................................ 10 AGND .......................................................................................... 20 Absolute Maximum Ratings .......................................................... 12 ODGND ...................................................................................... 20 Thermal Resistance .................................................................... 12 SIF REFP, SIF REFCM, and SIF REFN ................................ 20 Thermal Conditions ................................................................... 12 SIF IN1 and SIF IN2 ................................................................ 20 ESD Caution ................................................................................ 12 SIF PGA REF ............................................................................ 20 Pin Configuration and Function Descriptions ........................... 13 ISET .............................................................................................. 20 Typical Performance Characteristics ........................................... 16 Functional Descriptions ................................................................ 21 Terminology .................................................................................... 18 SIF Processor ............................................................................... 21 Pin Functions .................................................................................. 19 Master Clock Oscillator ............................................................. 21 SDIN0, SDIN1, SDIN2, and SDIN3/SPDIF IN0 ................... 19 2 I C Interface ................................................................................ 22 LRCLK0, BCLK0, LRCLK1, BCLK1, LRCLK2, and BCLK2 19 ADC Inputs ................................................................................. 22 SDO0/AD0 .................................................................................. 19 2 I S Digital Audio Inputs ............................................................ 22 SPDIF OUT (SDO1) ................................................................. 19 DAC Voltage Outputs ................................................................ 23 MCLKI/XIN ................................................................................ 19 PWM Outputs ............................................................................ 24 XOUT ........................................................................................... 19 Headphone Outputs ................................................................... 24 MCLK OUT ............................................................................... 19 2 I S Digital Audio Outputs ......................................................... 24 SDA ............................................................................................... 19 S/PDIF Input/Output ................................................................. 25 SCL ............................................................................................... 20 Hardware Mute Control ............................................................ 25 MUTE .......................................................................................... 20 Audio Processor ......................................................................... 25 RESET .......................................................................................... 20 Graphical Programming Environment ................................... 25 AUXIN1L, AUXIN2L, AUXIN1R, and AUXIN2R ................ 20 Application Layer ....................................................................... 25 AUXOUT1L, AUXOUT2L, AUXOUT3L, AUXOUT4L, Loading a Custom Audio Processing Flow ............................. 26 AUXOUT1R, AUXOUT2R, AUXOUT3R, and AUXOUT4R ....................................................................................................... 20 Outline Dimensions ....................................................................... 28 HPOUT1L, HPOUT2L, HPOUT1R, and HPOUT2R .......... 20 Ordering Guide .......................................................................... 28 PLL LF ......................................................................................... 20 Change to Hardware Mute Control, Graphical Programming REVISION HISTORY Environment, and Application Layer Sections ........................... 25 7/09Rev. A to Rev. B Changes to Ordering Guide .......................................................... 28 Added Advantiv Logo ...................................................................... 1 11/08Revision A: Initial Version Change to PWM Outputs Section ................................................ 24 Rev. B Page 2 of 28