Blackfin Embedded Processor ADSP-BF539/ADSP-BF539F External memory controller with glueless support FEATURES for SDRAM, SRAM, flash, and ROM Up to 533 MHz high performance Blackfin processor Flexible memory booting options from SPI and external Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs, memory 40-bit shifter PERIPHERALS RISC-like register and instruction model for ease of programming and compiler friendly support Parallel peripheral interface (PPI), supporting ITU-R 656 Advanced debug, trace, and performance monitoring video data formats Wide range of operating voltages see Operating Conditions 4 dual-channel, full-duplex synchronous serial ports, 2 on Page 26 supporting 16 stereo I S channels Qualified for automotive applications 2 DMA controllers supporting 26 peripheral DMAs Programmable on-chip voltage regulator 4 memory-to-memory DMAs 316-ball Pb-free CSP BGA package Controller area network (CAN) 2.0B controller Media transceiver (MXVR) for connection MEMORY to a MOST network 148K bytes of on-chip memory 3 SPI-compatible ports 16K bytes of instruction SRAM/cache Three 32-bit timer/counters with PWM support 64K bytes of instruction SRAM 3 UARTs with support for IrDA 32K bytes of data SRAM 2 2 TWI controllers compatible with I C industry standard 32K bytes of data SRAM/cache Up to 38 general-purpose I/O pins (GPIO) 4K bytes of scratchpad SRAM Up to 16 general-purpose flag pins (GPF) Optional 8M bit parallel flash with boot option Real-time clock, watchdog timer, and 32-bit core timer Memory management unit providing memory protection On-chip PLL capable of frequency multiplication Debug/JTAG interface VOLTAGE REGULATOR JTAG TEST AND EMULATION PERIPHERAL ACCESS BUS TWI0-1 INTERRUPT WATCHDOG CONTROLLER B TIMER CAN 2.0B GPIO PORT DMA CORE RTC BUS 2 C MXVR PPI DMA L1 INSTRUCTION L1 DATA DMA SPI1-2 MEMORY MEMORY CONTROLLER1 CONTROLLER 0 GPIO GPIO TIMER0-2 PORT PORT D F UART1-2 DMA DMA CORE DMA EXTERNAL BUS 1 SPI0 DMA CORE BUS 0 BUS 0 EXTERNAL BUS 1 GPIO SPORT2-3 PORT UART0 E EXTERNAL PORT FLASH, SDRAM CONTROL SPORT0-1 16 8M BIT PARALLEL FLASH BOOT ROM (See Table 1) Figure 1. Functional Block Diagram Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc. Rev. F Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Specifications subject to change without notice. No license is granted by implication Tel: 781.329.4700 2013 Analog Devices, Inc. All rights reserved. or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com BUS 1 DMA ACCESS DMA ACCESS BUS 0 PERIPHERALACCESS BUSADSP-BF539/ADSP-BF539F TABLE OF CONTENTS Features ................................................................. 1 Booting Modes ................................................... 16 Memory ................................................................ 1 Instruction Set Description .................................... 17 Peripherals ............................................................. 1 Development Tools .............................................. 17 General Description ................................................. 3 Example Connections and Layout Considerations ....... 18 Low Power Architecture ......................................... 3 MXVR Board Layout Guidelines ............................. 18 System Integration ................................................ 3 Voltage Regulator Layout Guidelines ....................... 19 ADSP-BF539/ADSP-BF539F Processor Peripherals ....... 3 Additional Information ........................................ 20 Blackfin Processor Core .......................................... 4 Related Signal Chains ........................................... 20 Memory Architecture ............................................ 5 Pin Descriptions .................................................... 21 DMA Controllers .................................................. 8 Specifications ........................................................ 26 Real-Time Clock ................................................... 9 Operating Conditions ........................................... 26 Watchdog Timer .................................................. 9 Electrical Characteristics ....................................... 27 Timers ............................................................... 9 Absolute Maximum Ratings ................................... 30 Serial Ports (SPORTs) .......................................... 10 ESD Sensitivity ................................................... 30 Serial Peripheral Interface (SPI) Ports ...................... 10 Package Information ............................................ 30 2-Wire Interface ................................................. 10 Timing Specifications ........................................... 31 UART Ports ...................................................... 10 Output Drive Currents ......................................... 50 Programmable I/O Pins ........................................ 11 Test Conditions .................................................. 52 Parallel Peripheral Interface ................................... 12 Thermal Characteristics ........................................ 55 Controller Area Network (CAN) Interface ................ 12 316-Ball CSP BGA Ball Assignment ........................... 56 Media Transceiver MAC layer (MXVR) ................... 13 Outline Dimensions ................................................ 59 Dynamic Power Management ................................ 13 Surface-Mount Design .......................................... 59 Voltage Regulation .............................................. 15 Ordering Guide ..................................................... 60 Clock Signals ..................................................... 15 REVISION HISTORY 10/13Rev. E to Rev. F Updated Development Tools .................................... 17 Added notes to Table 32 in Serial PortsEnable and Three-State .......................... 43 Added Timer Clock Timing ...................................... 48 Revised Timer Cycle Timing ..................................... 48 To view product/process change notifications (PCNs) related to this data sheet revision, please visit the processors product page on the www.analog.com website and use the View PCN link. Rev. F Page 2 of 60 October 2013