Blackfin+ Core Embedded Processor ADSP-BF700/701/702/703/704/705/706/707 FEATURES MEMORY Blackfin+ core with up to 400 MHz performance 136 kB L1 SRAM with multi-parity-bit protection (64 kB instruction, 64 kB data, 8 kB scratchpad) Dual 16-bit or single 32-bit MAC support per cycle Large on-chip L2 SRAM with ECC protection 16-bit complex MAC and many other instruction set enhancements 256 kB, 512 kB, 1 MB variants Instruction set compatible with previous Blackfin products On-chip L2 ROM (512 kB) Low-cost packaging L3 interface (CSP BGA only) optimized for lowest system power, providing 16-bit interface to DDR2 or LPDDR DRAM 88-Lead LFCSP VQ (QFN) package (12 mm 12 mm), devices (up to 200 MHz) RoHS compliant Security and one-time-programmable memory 184-Ball CSP BGA package (12 mm 12 mm 0.8 mm pitch), RoHS compliant Crypto hardware accelerators Low system power with < 100 mW core domain power at Fast secure boot for IP protection 400 MHz (< 0.25 mW/MHz) at 25C T JUNCTION memDMA encryption/decryption for fast run-time security AEC-Q100 qualified for automotive applications PERIPHERALS FEATURES See Figure 1, Processor Block Diagram and Table 1, Processor Comparison SYSTEM CONTROL BLOCKS PERIPHERALS 1 TWI EMULATOR PLL & POWER FAULT EVENT WATCHDOG TEST & CONTROL MANAGEMENT MANAGEMENT CONTROL 8 TIMER 1 COUNTER 2 CAN L2 MEMORY UP TO 2 UART 1M BYTE SRAM 512K BYTE B ROM ECC-PROTECTED SPI HOST PORT (& DMA MEMORY 136K BYTE PARITY BIT PROTECTED 2x QUAD SPI PROTECTION) GPIO L1 SRAM INSTRUCTION/DATA 1x DUAL SPI 2 SPORT 1 MSI SYSTEM FABRIC (SD/SDIO) 1 PPI EXTERNAL ANALOG BUS HARDWARE SUB STATIC MEMORY INTERFACES FUNCTIONS SYSTEM CONTROLLER MEMORY OTP SYSTEM PROTECTION 2 CRC PROTECTION 3 MDMA MEMORY STREAMS HADC CRYPTO ENGINE (SECURITY) DYNAMIC MEMORY CONTROLLER 1 RTC LPDDR 1 USB 2.0 HS OTG 16 DDR2 Figure 1. Processor Block Diagram Blackfin, Blackfin+, and the Blackfin logo are registered trademarks of Analog Devices, Inc. Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Specifications subject to change without notice. No license is granted by implication Tel: 781.329.4700 2019 Analog Devices, Inc. All rights reserved. or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.comADSP-BF700/701/702/703/704/705/706/707 TABLE OF CONTENTS Features . 1 12 mm 12 mm 88-Lead LFCSP (QFN) Signal Descriptions . 30 Peripherals Features . 1 GPIO Multiplexing for 12 mm 12 mm 88-Lead Memory 1 LFCSP (QFN) . 35 Table of Contents . 2 ADSP-BF70x Designer Quick Reference 37 Revision History 2 Specifications 49 General Description . 3 Operating Conditions . 49 Blackfin+ Processor Core 4 Electrical Characteristics . 52 Instruction Set Description . 5 HADC 57 Processor Infrastructure . 5 Absolute Maximum Ratings . 57 Memory Architecture 7 ESD Sensitivity . 57 Security Features 8 Timing Specifications . 58 Security Features Disclaimer 8 Output Drive Currents . 100 Processor Safety Features 9 Test Conditions 102 Additional Processor Peripherals 10 Environmental Conditions 104 Power and Clock Management . 12 ADSP-BF70x 184-Ball CSP BGA Ball Assignments System Debug 15 (Numerical by Ball Number) 105 Development Tools . 15 ADSP-BF70x 12 mm 12 mm 88-Lead LFCSP (QFN) Lead Assignments (Numerical by Lead Number) 108 Additional Information 16 Outline Dimensions 111 Related Signal Chains 16 Surface-Mount Design 112 ADSP-BF70x Detailed Signal Descriptions . 17 Automotive Products 113 184-Ball CSP BGA Signal Descriptions . 21 Ordering Guide . 114 GPIO Multiplexing for 184-Ball CSP BGA 28 REVISION HISTORY 2/2019Rev. C to Rev. D Deleted Package Information (Figure 7 and Table 27) in Specifications 49 Changes to TWI0VSEL Settings and VDD EXT/VBUSTWI . 50 Changes to Test Conditions . 102 Changes to Output Enable Time Measurement 102 Changes to Output Disable Time Measurement . 102 Changes to Output Enable/Disable 102 Changes to Automotive Products 113 Rev. D Page 2 of 114 February 2019