Rail-to-Rail, Very Fast, 2.5 V to 5.5 V, Single-Supply TTL/CMOS Comparator Data Sheet ADCMP603 FEATURES FUNCTIONAL BLOCK DIAGRAM V V CCI CCO Fully specified rail to rail at V = 2.5 V to 5.5 V CC Input common-mode voltage from 0.2 V to V + 0.2 V CC Low glitch CMOS-/TTL-compatible output stage V NONINVERTING P Complementary outputs INPUT Q OUTPUT 3.5 ns propagation delay TTL ADCMP603 12 mW at 3.3 V Q OUTPUT V INVERTING N Shutdown pin INPUT Single-pin control for programmable hysteresis and latch Power supply rejection > 50 dB 40C to +125C operation LE/HYS INPUT S INPUT DN APPLICATIONS Figure 1. High speed instrumentation Clock and data signal restoration Logic level shifting or translation Pulse spectroscopy High speed line receivers Threshold detection Peak and zero-crossing detectors High speed trigger circuitry Pulse-width modulators Current-/voltage-controlled oscillators Automatic test equipment (ATE) GENERAL DESCRIPTION The device passes 4.5 kV HBM ESD testing and the absolute The ADCMP603 is a very fast comparator fabricated on maximum ratings include current limits for all pins. XFCB2, an Analog Devices, Inc., proprietary process. This comparator is exceptionally versatile and easy to use. Features The complementary TTL-/CMOS-compatible output stage is include an input range from VEE 0.5 V to VCC + 0.2 V, low noise designed to drive up to 5 pF with full timing specs and to degrade complementary TTL-/CMOS-compatible output drivers, latch in a graceful and linear fashion as additional capacitance is added. inputs with adjustable hysteresis and a shutdown input. The comparator input stage offers robust protection against large input overdrive, and the outputs do not phase reverse when the The device offers 3.5 ns propagation delay with 10 mV valid input signal range is exceeded. Latch and programmable overdrive on 4 mA typical supply current. hysteresis features are also provided with a unique single-pin A flexible power supply scheme allows the device to operate control option. with a single +2.5 V positive supply and a 0.5 V to +2.8 V The ADCMP603 is available in a 12-lead LFCSP. input signal range up to a +5.5 V positive supply with a 0.5 V to +5.8 V input signal range. Split input/output supplies with no sequencing restrictions support a wide input signal range while still allowing independent output swing control and power savings. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20062016 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 05915-001ADCMP603 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Application Information ................................................................ 10 Applications ....................................................................................... 1 Power/Ground Layout and Bypassing ..................................... 10 Functional Block Diagram .............................................................. 1 TTL-/CMOS-Compatible Output Stage ................................. 10 General Description ......................................................................... 1 Using/Disabling the Latch Feature ........................................... 10 Revision History ............................................................................... 2 Optimizing Performance ........................................................... 11 Specifications ..................................................................................... 3 Comparator Propagation Delay Dispersion ........................... 11 Electrical Characteristics ............................................................. 3 Comparator Hysteresis .............................................................. 11 Timing Information ......................................................................... 5 Crossover Bias Point .................................................................. 12 Absolute Maximum Ratings ............................................................ 6 Minimum Input Slew Rate Requirement ................................ 12 Thermal Resistance ...................................................................... 6 Typical Application Circuits ......................................................... 13 ESD Caution .................................................................................. 6 Outline Dimensions ....................................................................... 14 Pin Configuration and Function Descriptions ............................. 7 Ordering Guide .......................................................................... 14 Typical Performance Characteristics ............................................. 8 REVISION HISTORY 4/16Rev. 0 to Rev. A Changes to Figure 3 and Table 5 ..................................................... 7 Updated Outline Dimensions ....................................................... 14 Changes to Ordering Guide .......................................................... 14 10/06Revision 0: Initial Version Rev. A Page 2 of 16