Complete, 12-Bit, 45 MHz CCD Signal Processor ADDI7100 FEATURES GENERAL DESCRIPTION Pin-compatible upgrade for the AD9945 The ADDI7100 is a complete analog signal processor for charge- 45 MHz correlated double sampler (CDS) with variable gain coupled device (CCD) applications. It features a 45 MHz, 6 dB to 42 dB, 10-bit variable gain amplifier (VGA) single-channel architecture designed to sample and condition Low noise optical black clamp circuit the outputs of interlaced and progressive scan area CCD arrays. Preblanking function The signal chain for the ADDI7100 consists of a correlated double 12-bit, 45 MHz ADC sampler (CDS), a digitally controlled variable gain amplifier No missing codes guaranteed (VGA), a black level clamp, and a 12-bit ADC. 3-wire serial digital interface The internal registers are programmed through a 3-wire serial 3 V single-supply operation digital interface. Programmable features include gain adjustment, Space-saving, 32-lead, 5 mm 5 mm LFCSP black level adjustment, input clock polarity, and power-down modes. The ADDI7100 operates from a single 3 V power supply, APPLICATIONS typically dissipates 125 mW, and is packaged in a space-saving, Digital still cameras 32-lead LFCSP. Digital video camcorders PC cameras Portable CCD imaging devices CCTV cameras FUNCTIONAL BLOCK DIAGRAM REFT REFB PBLK ADDI7100 BAND GAP DRVDD REFERENCE 3dB, 0dB, DRVSS +3dB, +6dB 6dB TO 42dB 12 12-BIT DOUT CCDIN CDS VGA D0 TO D11 ADC CLP AVDD 10 CLPOB AVSS CONTROL REGISTERS DVDD DIGITAL INTERNAL INTERFACE TIMING DVSS VD SL SCK SDATA SHP SHD DATACLK Figure 1. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 20082010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 07608-001ADDI7100 TABLE OF CONTENTS Features .............................................................................................. 1 Terminology .................................................................................... 11 Applications ....................................................................................... 1 Circuit Description and Operation .............................................. 12 General Description ......................................................................... 1 DC Restore .................................................................................. 12 Functional Block Diagram .............................................................. 1 Correlated Double Sampler (CDS) .......................................... 12 Revision History ............................................................................... 2 Optical Black Clamp .................................................................. 12 Specif icat ions ..................................................................................... 3 Analog-to-Digital Converter (ADC) ....................................... 13 General Specifications ................................................................. 3 Variable Gain Amplifier (VGA) ............................................... 13 Digital Specifications ................................................................... 3 Digital Data Outputs .................................................................. 13 System Specifications ................................................................... 4 Applications Information .............................................................. 14 Timing Specifications .................................................................. 5 Initial Power-On Sequence ....................................................... 15 Absolute Maximum Ratings ............................................................ 7 Grounding and Decoupling Recommendations .................... 15 Thermal Resistance ...................................................................... 7 Serial Interface Timing .................................................................. 16 ESD Caution .................................................................................. 7 Complete Register Listing ............................................................. 17 Pin Configuration and Function Descriptions ............................. 8 Outline Dimensions ....................................................................... 19 Typical Performance Characteristics ............................................. 9 Ordering Guide .......................................................................... 19 Equivalent Input Circuits .............................................................. 10 REVISION HISTORY 6/10Rev. B to Rev. C Changes to 0x0D Description and 0xFF Description in Table 8 .............................................................................................. 18 9/09Rev. A. to Rev. B Changes to Features Section............................................................ 1 Changed Power-Down Mode to Full Standby Mode, Table 1 .... 3 Moved Timing Diagrams Section .................................................. 5 Changes to Table 4, Figure 3, and Figure 4 ................................... 5 Changes to Figure 9 Caption ......................................................... 10 Changes to Optical Black Clamp Section .................................... 12 Changes to Initial Power-On Sequence Section ......................... 15 Changes to Figure 16 ...................................................................... 16 Changes to Table 8 .......................................................................... 17 2/09Rev. 0 to Rev. A Changes to Serial Interface Timing Section ................................ 16 Changes to Figure 16 and Figure 17 ............................................. 16 10/08Revision 0: Initial Version Rev. C Page 2 of 20