14-Bit, 170 MSPS/250 MSPS, JESD204B, Dual Analog-to-Digital Converter Data Sheet AD9250 FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD DRVDD DVDD AGND DGND DRGND JESD204B Subclass 0 or Subclass 1 coded serial digital outputs Signal-to-noise ratio (SNR) = 70.6 dBFS at 185 MHz AIN and AD9250 250 MSPS VIN+A PIPELINE JESD204B SERDOUT0 Spurious-free dynamic range (SFDR) = 88 dBc at 185 MHz 14-BIT ADC INTERFACE VINA CML, TX AIN and 250 MSPS OUTPUTS VCM HIGH SPEED Total power consumption: 711 mW at 250 MSPS SERIALIZERS SERDOUT1 VIN+B PIPELINE 14-BIT ADC 1.8 V supply voltages VINB Integer 1-to-8 input clock divider CMOS DIGITAL CONTROL PDWN REGISTERS INPUT Sample rates of up to 250 MSPS IF sampling frequencies of up to 400 MHz SYSREF SYNCINB CLOCK Internal analog-to-digital converter (ADC) voltage reference GENERATION CMOS FDA CLK FAST DIGITAL DETECT FDB RFCLK OUTPUT Flexible analog input range CMOS DIGITAL INPUT/OUTPUT 1.4 V p-p to 2.0 V p-p (1.75 V p-p nominal) ADC clock duty cycle stabilizer (DCS) SDIO SCLK CS RST 95 dB channel isolation/crosstalk Figure 1. Serial port control Energy saving power-down modes PRODUCT HIGHLIGHTS APPLICATIONS 1. Integrated dual, 14-bit, 170 MSPS/250 MSPS ADC. 2. The configurable JESD204B output block supports up to Diversity radio systems 5 Gbps per lane. Multimode digital receivers (3G) 3. An on-chip, phase-locked loop (PLL) allows users to provide TD-SCDMA, WiMAX, W-CDMA, CDMA2000, GSM, EDGE, LTE a single ADC sampling clock the PLL multiplies the ADC DOCSIS 3.0 CMTS upstream receive paths sampling clock to produce the corresponding JESD204B HFC digital reverse path receivers data rate clock. I/Q demodulation systems 4. Support for an optional RF clock input to ease system board Smart antenna systems design. Electronic test and measurement equipment 5. Proprietary differential input maintains excellent SNR Radar receivers performance for input frequencies of up to 400 MHz. COMSEC radio architectures 6. Operation from a single 1.8 V power supply. IED detection/jamming systems General-purpose software radios 7. Standard serial port interface (SPI) that supports various Broadband data applications product features and functions such as controlling the clock DCS, power-down, test modes, voltage reference mode, over range fast detection, and serial output configuration. This product may be protected by one or more U.S. or international patents. Rev. E Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20122017 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com 10559-001AD9250 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 JESD204B Overview .................................................................. 25 Applications ....................................................................................... 1 JESD204B Synchronization Details ......................................... 26 Functional Block Diagram .............................................................. 1 Link Setup Parameters ............................................................... 26 Product Highlights ........................................................................... 1 Frame and Lane Alignment Monitoring and Correction ..... 30 Revision History ............................................................................... 3 Digital Outputs and Timing ..................................................... 30 General Description ......................................................................... 4 ADC Overrange and Gain Control .......................................... 32 Specifications ..................................................................................... 5 ADC Overrange (OR) ................................................................ 32 ADC DC Specifications ............................................................... 5 Gain Switching ............................................................................ 32 ADC AC Specifications ............................................................... 6 DC Correction ................................................................................ 33 Digital Specifications ................................................................... 7 DC Correction Bandwidth ........................................................ 33 Switching Specifications .............................................................. 9 DC Correction Readback .......................................................... 33 Timing Specifications ................................................................ 10 DC Correction Freeze ................................................................ 33 Absolute Maximum Ratings .......................................................... 11 DC Correction (DCC) Enable Bits .......................................... 33 Thermal Characteristics ............................................................ 11 Serial Port Interface (SPI) .............................................................. 34 ESD Caution ................................................................................ 11 Configuration Using the SPI ..................................................... 34 Pin Configuration and Function Descriptions ........................... 12 Hardware Interface ..................................................................... 34 Typical Performance Characteristics ........................................... 14 SPI Accessible Features .............................................................. 35 Equivalent Circuits ......................................................................... 18 Memory Map .................................................................................. 36 Theory of Operation ...................................................................... 20 Reading the Memory Map Register Table ............................... 36 ADC Architecture ...................................................................... 20 Memory Map Register Table ..................................................... 37 Analog Input Considerations .................................................... 20 Memory Map Register Description ......................................... 41 Voltage Reference ....................................................................... 21 Applications Information .............................................................. 42 Clock Input Considerations ...................................................... 21 Design Guidelines ...................................................................... 42 Power Dissipation and Standby Mode ..................................... 24 SPI Initialization Sequence ....................................................... 42 Digital Outputs ............................................................................... 25 Outline Dimensions ....................................................................... 45 JESD204B Transmit Top Level Description ............................ 25 Ordering Guide .......................................................................... 45 Rev. E Page 2 of 45